Scheduling of Wafer Test Processes in Semiconductor Manufacturing

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dc.contributor.advisor Sturges, Robert H. Jr. en_US
dc.contributor.advisor Ellis, Kimberly P. en_US
dc.contributor.advisor Bish, Ebru K. en_US
dc.contributor.author Lu, Yufeng en_US
dc.date.accessioned 2011-08-06T16:07:35Z
dc.date.available 2011-08-06T16:07:35Z
dc.date.issued 1997-04-14 en_US
dc.identifier.other etd-11142001-173857 en_US
dc.identifier.uri http://hdl.handle.net/10919/10153
dc.description.abstract Scheduling is one of the most important issues in the planning of manufacturing systems. This research focuses on solving the test scheduling problem which arises in semiconductor manufacturing environment. Semiconductor wafer devices undergo a series of test processes conducted on computer-controlled test stations at various temperatures. A test process consists of both setup operations and processing operations on the test stations. The test operations occur in a specified order on the wafer devices, resulting in precedence constraints for the schedule. Furthermore, the assignment of the wafer devices to test stations and the sequence in which they are processed affects the time required to finish the test operations, resulting in sequence dependent setup times. The goal of this research is to develop a realistic model of the semiconductor wafer test scheduling problem and provide heuristics for scheduling the precedence constrained test operations with sequence dependent setup times. A mathematical model is presented and two heuristics are developed to solve the scheduling problem with the objective of minimizing the makespan required to test all wafer devices on a set of test stations. The heuristic approaches generate a sorted list of wafer devices as a dispatching sequence and then schedule the wafer lots on test stations in order of appearance on the list. An experimental analysis and two case studies are presented to validate the proposed solution approaches. In the two case studies, the heuristics are applied to actual data from a semiconductor manufacturing facility. The results of the heuristic approaches are compared to the actual schedule executed in the manufacturing facility. For both the case studies, the proposed solution approaches decreased the makespan by 23-45% compared to the makespan of actual schedule executed in the manufacturing facility. The solution approach developed in this research can be integrated with the planning software of a semiconductor manufacturing facility to improve productivity. en_US
dc.format.medium ETD en_US
dc.publisher Virginia Tech en_US
dc.relation.haspart Thesis.pdf en_US
dc.rights The authors of the theses and dissertations are the copyright owners. Virginia Tech's Digital Library and Archives has their permission to store and provide access to these works. en_US
dc.source.uri http://scholar.lib.vt.edu/theses/available/etd-11142001-173857 en_US
dc.subject wafer test scheduling en_US
dc.subject heuristic en_US
dc.subject semiconductor test en_US
dc.title Scheduling of Wafer Test Processes in Semiconductor Manufacturing en_US
dc.type Thesis en_US
dc.contributor.department Industrial and Systems Engineering en_US
dc.description.degree MS en_US

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