Analysis and design of a novel controller architecture and design methodology for speed control of switched reluctance motors

This paper presents a novel controller architecture and speed control design methodology suitable for low cost, low performance switched reluctance motor drives. By utilizing inexpensive components in a simple, compact architecture, a low cost controller is developed which achieves a performance level similar to many high performance controllers. A speed control design methodology is established and analyzed based on the linearized small signal model of the switched reluctance motor. This unique control methodology is simple and provides a starting point for further research into speed/current controller parameter design for switched reluctance motors. The analysis, design and realization of the speed controller are presented. The derivation of the design methodology for speed controlled, switched reluctance motor drives is discussed, along with computer simulations for verification. Experimental results utilizing the proposed architecture and design methodology verify the control design and performance capabilities of the speed controller system.