The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated.

Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary.

This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms.