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dc.date.accessioned2019-02-26T22:24:02Z
dc.date.available2019-02-26T22:24:02Z
dc.date.issued2018-07-03
dc.identifier.urihttp://hdl.handle.net/10919/87842
dc.description.abstractIn a multi-phase power converter using a phase-locked loop (PLL) arrangement for interleaving of pulse frequency modulated (PFM) pulses of the respective phases, improved transient response, improved stability of high bandwidth output voltage feedback loop, guaranteed stability of the PLL loop and avoidance of jittering and phase cancellation issues are achieved by anchoring the bandwidth at the frequency of peak phase margin. This methodology is applicable to multi-phase power conveners of any number of phases and any known or foreseeable topology for individual phases and is not only applicable to power converters operating under constant on-time control, but is extendable to ramp pulse modulation (RPM) control and hysteresis control. Interleaving of pulses from all phases is simplified through use of phase managers with a reduced number of PLLS using hybrid interleaving arrangements that do not exhibit jittering even when ripple is completely canceled.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherUnited States Patent and Trademark Office
dc.titleHybrid interleaving structure with adaptive phase locked loop for variable frequency controlled switching converter
dc.typePatent
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.contributor.departmentCenter for Power Electronics Systems (CPES)en_US
dc.identifier.urlhttp://pimg-fpiw.uspto.gov/fdd/07/130/100/0.pdf
dc.date.accessed2019-02-15
dc.type.dcmitypeText
dc.contributor.assigneeVirginia Tech Intellectual Properties, Inc.
dc.contributor.inventorLi, Qiang
dc.contributor.inventorLiu, Pei-Hsin
dc.contributor.inventorLee, Fred C.
dc.date.filed2015-03-31
dc.identifier.applicationnumber14674680
dc.subject.cpcG05F1/56
dc.subject.cpcH02M3/1584
dc.subject.cpcH02M2003/1586
dc.subject.cpcH03L7/06
dc.type.patenttypeutility
dc.identifier.patentnumber10013007


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