Model-Driven Validation of SystemC Designs

dc.contributor.authorPatel, Hiren D.en
dc.contributor.authorShukla, Sandeep K.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2012-08-24T12:06:49Zen
dc.date.available2012-08-24T12:06:49Zen
dc.date.issued2008-04-21en
dc.date.updated2012-08-24T12:06:49Zen
dc.description.abstractFunctional test generation for dynamic validation of current system level designs is a challenging task. Manual test writing or automated random test generation techniques are often used for such validation practices. However, directing tests to particular reachable states of a SystemC model is often difficult, especially when these models are large and complex. In this work, we present a model-driven methodology for generating directed tests that take the SystemC model under validation to specific reachable states. This allows the validation to uncover very specific scenarios which lead to different corner cases. Our formal modeling is done entirely within the Microsoft SpecExplorer tool to formally describe the specification of the system under validation in the formal notation of AsmL. We also exploit SpecExplorer's abilities for state space exploration for our test generation, and its APIs for connecting the model to real programs to drive the validation of SystemC models with the generated test cases.en
dc.description.versionPublished versionen
dc.format.mimetypeapplication/pdfen
dc.identifier.citationEURASIP Journal on Embedded Systems. 2008 Apr 21;2008(1):519474en
dc.identifier.doihttps://doi.org/10.1155/2008/519474en
dc.identifier.urihttp://hdl.handle.net/10919/18904en
dc.language.isoenen
dc.rightsCreative Commons Attribution 4.0 Internationalen
dc.rights.holderHiren D Patel et al.; licensee BioMed Central Ltd.en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.titleModel-Driven Validation of SystemC Designsen
dc.title.serialEURASIP Journal on Embedded Systemsen
dc.typeArticle - Refereeden
dc.type.dcmitypeTexten

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