Designing a Compiler for a Distributed Memory Parallel Computing System

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dc.contributor.authorBennett, Sidney Pageen
dc.contributor.committeechairBaker, James M. Jr.en
dc.contributor.committeememberDavis, Nathaniel J. IVen
dc.contributor.committeememberArthur, James D.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2011-08-06T14:45:02Zen
dc.date.adate2004-01-22en
dc.date.available2011-08-06T14:45:02Zen
dc.date.issued2003-11-01en
dc.date.rdate2004-01-22en
dc.date.sdate2004-01-06en
dc.description.abstractThe SCMP processor presents a unique approach to processor design: integrating multiple processors, a network, and memory onto a single chip. The benefits to this design include a reduction in overhead incurred by synchronization, communication, and memory accesses. To properly determine its effectiveness, the SCMP architecture must be exercised under a wide variety of workloads, creating the need for a variety of applications. A compiler can relieve the time spent developing these applications by allowing the use of languages such as C and Fortran. However, compiler development is a research area in its own right, requiring extensive knowledge of the architecture to make good use of its resources. This thesis presents the design and implementation of a compiler for the SCMP architecture. The thesis includes an in-depth analysis of SCMP and the necessary design choices for an effective compiler using the SUIF and MachSUIF toolsets. Two optimizations passes are included in the discussion: partial redundancy elimination and instruction scheduling. While these optimizations are not specific to parallel computing, architectural considerations must still be made to properly implement the algorithms within the SCMP compiler. These optimizations yield an overall reduction in execution time of 15-36%.en
dc.description.degreeMaster of Scienceen
dc.format.mediumETDen
dc.identifier.otheretd-01062004-132011en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-01062004-132011en
dc.identifier.urihttp://hdl.handle.net/10919/9684en
dc.publisherVirginia Techen
dc.relation.haspartsibennet_thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSUIFen
dc.subjectCompiler Designen
dc.subjectParallel Computingen
dc.subjectOptimizationen
dc.subjectMachSUIFen
dc.subjectMultithreadingOptimizationen
dc.subjectParallel Computingen
dc.subjectMultithreadingen
dc.titleDesigning a Compiler for a Distributed Memory Parallel Computing Systemen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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