Browsing by Author "Bollinger, S. Wayne"
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- Hierarchical test generation for CMOS circuitsBollinger, S. Wayne (Virginia Tech, 1992-03-05)As advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach.
- Processor and link assignment using simulated annealingBollinger, S. Wayne (Virginia Tech, 1988-05-17)Advances in VLSI technology have made possible a new generation of multicomputer systems that contain hundreds or thousands of processors and offer a combined processing power far beyond that possible in a single processor machine. Multicomputers can be used to solve a variety of computationally intensive applications, but they introduce the problem of handling communication between concurrent processes. In the design of multicomputer systems, the scheduling and mapping of a parallel algorithm onto a host architecture has a critical impact on overall system performance. The problem of how to best assign the resources of a host multicomputer system to the cooperating tasks of a parallel application program is known as the mapping problem. In this research we develop a graph-based solution to both aspects of the mapping problem using the simulated annealing optimization heuristic. A two phase mapping strategy is formulated: I) process annealing assigns parallel processes to processing nodes, and 2) connection annealing schedules traffic connections on network data links so that interprocess communication conflicts are minimized. To evaluate the quality of generated mappings, cost functions suitable for simulated annealing are derived that accurately quantify communication overhead. Communication efficiency is formulated to measure the quality of assignments when the optimal mapping is unknown. Application examples are presented using the hypercube as a host architecture, with host graphs containing up to 512 nodes. The influence of various parameters on the annealing algorithms is investigated, and results for several image graphs are presented.