VTechWorks Repository :: Browsing by Author "Dimarino, Christina Marie"

Browsing by Author "Dimarino, Christina Marie"

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Brain Signal Quantification and Functional Unit Analysis in Fluorescent Imaging Data by Unsupervised Learning
Mi, Xuelong (Virginia Tech, 2024-06-04)
Optical recording of various brain signals is becoming an indispensable technique for biological studies, accelerated by the development of new or improved biosensors and microscopy technology. A major challenge in leveraging the technique is to identify and quantify the rich patterns embedded in the data. However, existing methods often struggle, either due to their limited signal analysis capabilities or poor performance. Here we present Activity Quantification and Analysis (AQuA2), an innovative analysis platform built upon machine learning theory. AQuA2 features a novel event detection pipeline for precise quantification of intricate brain signals and incorporates a Consensus Functional Unit (CFU) module to explore interactions among potential functional units driving repetitive signals. To enhance efficiency, we developed BIdirectional pushing with Linear Component Operations (BILCO) algorithm to handle propagation analysis, a time-consuming step using traditional algorithms. Furthermore, considering user-friendliness, AQuA2 is implemented as both a MATLAB package and a Fiji plugin, complete with a graphical interface for enhanced usability. AQuA2's validation through both simulation and real-world applications demonstrates its superior performance compared to its peers. Applied across various sensors (Calcium, NE, and ATP), cell types (astrocytes, oligodendrocytes, and neurons), animal models (zebrafish and mouse), and imaging modalities (two-photon, light sheet, and confocal), AQuA2 consistently delivers promising results and novel insights, showcasing its versatility in fluorescent imaging data analysis.
Design and Testing of a SiC-based Solid-State Bypass Switch for 1 kV Power Electronics Building Blocks
Mutyala, Sri Naga Vinay (Virginia Tech, 2021-09-24)
Over the past two decades, power consumption has increased exponentially worldwide, posing new challenges to power grids to meet the load requirements. With this growing power demand, the need for efficient high-density medium-voltage (MV) power converters has increased to support flexible power distribution grids. The modular multilevel converters (MMC) became the most typical MV power converters in applications from 2010. This topology has many advantages, such as voltage scalability, excellent output performance, and low voltage ratings for switching devices. However, without the excellent reliability of the MMC, applications cannot reap these benefits. The MMC topology comprises several series-connected submodules (typically a half-bridge or a full-bridge inverter). As a result of increased switching devices, the converter becomes vulnerable since a single device fault can disrupt the whole converter operation. Therefore, fault-tolerant strategies to replace faulty SM with a redundant SM are developed using additional bypass switches. Conventionally TRIACs and vacuum switches are employed as bypass switches that operate in the range of 2-10 microseconds. Despite having performance advantages, MMCs are still not fully employed in aerospace and naval industries due to their enormous size. Many Power Electronics Building Blocks (PEBB) are proposed, with size optimization, as submodules for modular converters. The PEBB1000, a 1000 V- PEBB proposed by Dr. Jun Wang, achieved a significant size reduction of 80% with a novel switching cycle control (SCC) scheme. This novel control scheme requires high switching frequency and high di/dt-currents for MMC operation. Due to di/dt-rate limitations, TRIAC-based switch cannot perform bypass operation. Therefore, research work has been conducted on bypass switches for PEBB1000 using wide-bandgap SiC devices. This thesis presents the design of a SiC MOSFET-based bypass switch for PEBB1000 in MMC application. A detailed fault case analysis is presented to show the feasibility of the bypass operation for 90% PEBB-level faults. Significant variations in PEBB1000 bypass requirements are observed through SCC-based MMC simulations. Accordingly, a 1700 V, 100 A bypass switch has been designed using the anti-series topology of MOSFETs. Various specifications, such as 142 nanoseconds operation time, 500 nanoseconds bypass commutation time, and 277A transient current conduction capability, are validated through practical tests. Results prove that SiC-MOSFETs work better than TRIACs in high di/dt-current conduction and operation times. For future work, false-triggering endurance has to be analyzed for 1000 V switching voltage.
Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen
Dimarino, Christina Marie (Virginia Tech, 2019-01-03)
Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.
Design of a 405/430 kHz, 100 kW Transformer with Medium Voltage Insulation Sheets
Sharfeldden, Sharifa (Virginia Tech, 2023-07-27)
To achieve higher power density, converters and components must be able to handle higher voltage and current ratings at higher percentages of efficiency while also maintaining low cost and a compact footprint. To meet such demands, medium-voltage resonant converters have been favored by researchers for their ability to operate at higher switching frequencies. High frequency (HF) operation enables soft switching which, when achieved, reduces switching losses via either zero voltage switching (ZVS) or zero current switching (ZCS) depending on the converter topology. In addition to lower switching losses, the converter operates with low harmonic waveforms which produce less EMI compared to their hard switching counterparts. Finally, these resonant converters can be more compact because higher switching frequencies imply decreased volume of passive components. The passive component which benefits the most from this increased switching frequency is the transformer. The objective of this work is to design a >400 kHz, 100 kW transformer which will provide galvanic isolation in a Solid-State Transformer (SST) based PEBBs while maintaining high efficiency, high power density, and reduced size. This work aims to present a simplified design process for high frequency transformers, highlighting the trade-offs between co-dependent resonant converter and transformer parameters and how to balance them during the design process. This work will also demonstrate a novel high frequency transformer insulation design to achieve a partial discharge inception voltage (PDIV) of >10 kV.
Design of a Hybrid Unipolar Modulation Dual-Buck Inverter using Wide Bandgap Devices
Alcorn, Devon Montague (Virginia Tech, 2023-10-11)
Common mode performance is important for photovoltaic applications where the common mode voltage can become hazardous to people near the solar installation and can cause reliability concerns in inverters. The proposed dual-buck inverter uses hybrid unipolar modulation and a topology that is modified from the standard full-bridge dual-buck inverter to address the common mode voltage concerns. In the proposed design, the fast-switching side of the inverter is identical to a half-bridge dual-buck inverter, while the side that switches at line frequency uses a half-bridge of the standard H-bridge inverter topology. The motivation of this design is to realize the benefits of unipolar modulation and the dual-buck topology, while improving the poor common-mode voltage performance associated with unipolar modulation by utilizing hybrid switching. Unipolar switching has benefits which carry over to the hybrid switching scheme, such as reduced current ripple allowing use of smaller inductors. Additionally, the dual-buck topology enables the effective use of faster switches due to the elimination of dead time and reverse recovery concerns by using devices such as wide-bandgap GaN HEMTS and SiC Schottky diodes. The proposed inverter topology also realizes the benefits of the dual-buck topology while using half of the number of diodes and inductors compared to a standard full-bridge dual-buck inverter. The use of this modified dual-buck topology and hybrid unipolar modulation results in an inverter which has favorable common mode voltage characteristics. These characteristics indicate that this inverter would be useful in applications sensitive to common mode voltage concerns, such as photovoltaic applications. The performance of this topology using hybrid unipolar modulation is investigated using simulations and by creating and testing a 300-watt prototype inverter.
Design, Fabrication, Characterization, and Packaging of Gallium Oxide Power Diodes
Wang, Boyan (Virginia Tech, 2024-02-22)
Gallium Oxide (Ga2O3) is an ultra-wide bandgap semiconductor with a bandgap of 4.5–4.9 eV, which is larger than that of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN). A benefit of this ultra-wide bandgap is the high-temperature stability due to the low intrinsic carrier concentration. Another benefit is the high critical electric field (Ec), which is estimated to be from 6 MV/cm to 8 MV/cm in Ga2O3. This allows for a superior Baliga's figure of merit (BFOM) of unipolar Ga2O3 power devices, i.e., they potentially can achieve a smaller specific on-resistance (RON,SP) as compared to the Si, SiC, and GaN devices with the same breakdown voltage (BV). The above prospects make Ga2O3 devices the promising candidates for next-generation power electronics. This dissertation explores the design, fabrication, characterization, and packaging of vertical β-Ga2O3 Schottky barrier diodes (SBDs) and P-N diodes. The power SBDs allow for a small forward voltage and a fast switching speed; thus, it is ubiquitously utilized in power electronics systems. Meanwhile, the Ga2O3 power P-N diodes have the benefit of smaller leakage current, and the diode structure could be a building block for many advanced diodes and transistors. Hence, the study of Ga2O3 Schottky and P-N diodes is expected to provide the foundation for developing a series of Ga2O3 power devices. Firstly, vertical Ga2O3 Schottky and P-N diodes with a novel edge termination (ET), the multi-layer Nickel Oxide (NiO) junction termination extension (JTE), are fabricated on Ga2O3 substrates. This multi-JTE NiO structure decreases the peak electric field (Epeak) at the triple point of device edge when the Ga2O3 diodes are reversely biased. For SBDs, BV reach 2.5 kV, the 1-D junction field reaches 3.08 MV/cm, and the BFOM exceeds 1 GW/cm2. For P-N diodes, BV reaches 3.3 kV, the junction field reaches 4.2 MV/cm, and the BFOM reaches 2.6 GW/cm2. These results are among the highest in Ga2O3 power devices and are comparable to the state-of-the-art vertical GaN Schottky and P-N diodes. Notably, all these diodes are small-area devices. Secondly, large-area (3 mm×3 mm anode size) Ga2O3 Schottky and P-N diodes with high current capability are fabricated to explore the packaging, thermal management, and switching characteristics of Ga2O3 diodes. The same ET is applied for the large-area P-N diode. The fabricated large-area P-N diodes have a turn-on voltage of 2 V, a differential on-resistance (Ron) of 0.2 Ω, and they can reach at least 15 A when measured in the pulse mode. The BV of large-area Ga2O3 P-N diodes varies due to the fabrication non-uniformity, but the best device achieves a BV of 1.6 kV, standing among the highest values reported for large-area Ga2O3 diodes. Also, the large-area Ga2O3 SBDs with similar current rating but with a FP ET are fabricated mainly for the packaging and thermal management studies. Thirdly, medium-area Ga2O3 P-N diodes with a current over 1 A and a higher yield of BV are fabricated to evaluate the JTE's capacitance and switching characteristics. The JTE accounts for only ~11% of the junction capacitance of this 1 A diode, and the percentage is expected to be even smaller for higher-current diodes. The turn-on/off speed and reverse recovery time of the diode are comparable to commercial SiC Schottky barrier diodes under the on-wafer switching test. These results show the viability of NiO JTE for enabling a fast switching speed in high-voltage Ga2O3 power devices. Fourthly, the fabricated large-area Ga2O3 diodes are packaged using silver sintering as the die attach. The sintered silver joint has higher thermal conductivity (kT) and better reliability as compared to the solder joint. Due to the low kT of Ga2O3 material, junction-side-cooled (JSC) packaging configuration is necessary for Ga2O3 devices. For the packaged device, its junction-to-case thermal resistance (RθJC) is measured in the bottom-side-cooled (BSC) and junction-side-cooled (JSC) configuration by the transient dual interface method according to the JEDEC 51-14 standard. The RθJC of the junction- and bottom-cooled Ga2O3 SBD is measured to be 0.5 K/W and 1.43 K/W, respectively. The former RθJC is lower than that of similarly-rated commercial SiC SBDs. This manifests the significance of JSC packaging for the thermal management of Ga2O3 devices. Fifthly, to evaluate the electrothermal robustness of the packaged Ga2O3 devices, the surge current capability of JSC packaged Ga2O3 SBDs are measured. The Ga2O3 SBDs with proper packaging show high surge current capabilities. The double-side-cooled (DSC) large-area Ga2O3 SBDs can sustain a peak surge current over 60 A, with a ratio between the peak surge current and the rated current superior to that of similarly-rated commercial SiC SBDs. These results show the excellent ruggedness of Ga2O3 power devices. Finally, a Ga2O3 integrated diode module consisting of four single-diode sub-modules is designed and fabricated. For many power electronics applications, high current is desired; however, for emerging semiconductors, the current upscaling is difficult by directly increasing the device area because of the limitation of heat extraction capability and the limited material/processing yield. Here we explore the paralleling of multiple Ga2O3 P-N diodes to increase the current level. For each sub-module, the JSC packaging structure is used for heat extraction, and a metal post is sintered to the anode for electric field (E-field) management. RθJC is measured to be 1 W/K for each sub-module. On-board double-pulsed test is performed for both the sub-module and the full module. The sub-module and full module demonstrate 400 V, 10 A and 150 V, 70 A switching capabilities, respectively. This is the first demonstration of Ga2O3 power module and shows a promising approach to upscale of the power level of Ga2O3 power electronics. In addition to Ga2O3 device study, a research is conducted to explore the chip size (Achip) minimization for wide-bandgap (WBG) and ultra-wide bandgap (UWBG) power devices. Achip optimization is particularly critical for WBG and UWBG power devices and modules due to the high material cost. This work presents a new, holistic, electrothermal approach to optimize Achip for a given set of target specifications including BV, conduction current (I0), and switching frequency (f). The conduction and switching losses of the device are considered, as well as the heat dissipation in the chip and its package. For a given BV and I0, the optimal Achip, Wdr, and Ndr show strong dependence on f and thermal management. Our approach offers more accurate cost analysis and design guidelines for power modules. In summary, this dissertation covers the design, fabrication, characterization, and packaging of Ga2O3 Schottky and P-N diodes, with the aim to advance Ga2O3 devices to power electronics applications. This dissertation addresses many knowledge gaps on Ga2O3 devices, including the voltage upscaling (ET), current upscaling (large-area device fabrication, packaging, and thermal management), and their concurrence (module demonstration), as well as the circuit-level switching characterizations.
Double-Side Cooled 3.3 kV, 100 A SiC MOSFET Phase-Leg Modules for Traction Applications
Yuchi, Qingrui (Virginia Tech, 2024-08-20)
This thesis presents the development of a double-side cooled 3.3 kV, 100 A SiC MOSFET phase-leg power module for heavy-duty traction applications. Parasitic extraction and thermal simulations of the module showed a parasitic inductance of 2.89 nH and junction temperature of 108.3 °C at a heat flux of 156 W/cm² under a typical water-cooling condition. Electric field simulations identified high electric field stress at the module's outer surface edges exposed to air, posing a risk for partial discharge. To mitigate this risk, a solution that involves covering the critical point in an epoxy was proposed, analyzed, and validated through partial discharge inception voltage tests. Steps for fabricating the module are presented. Static electrical characterization of the fabricated module showed an average on-resistance of 31 mΩ and an average leakage current of 356 nA at VDS of 3 kV, which are similar to those of the unpackaged devices. The module with a double-side cooling design achieved an exceptional power density of 116.6 kW/cm³, more than twice that of any single-side cooled 3.3 kV SiC module. This makes it highly suitable for next-generation electric transportation systems that require high power density and efficient thermal management, such as electric trucks, railways, and eVTOL aircraft.
Electro-Thermal Device-Package Co-Design for a High-Temperature Ultra-Wide-Bandgap Gallium-Oxide Power Module
Lyon, Benjamin Peter (Virginia Tech, 2023-06-22)
Power electronic systems and components that can operate in environments with ambient temperatures exceeding 250 °C are needed for innovation in automotive, aerospace, and down-hole applications. With the imminent mass electrification of transportation and industry, the high-temperature electronics market value is anticipated to grow to $15 billion by the end of 2023. Conventionally, silicon (Si)-based converters are used in these applications; however, as operating temperatures continue to increase, the inherent limits of these systems are being met. The primary limitations for the high-temperature operation of semiconductor devices is the intrinsic carrier concentration, dictated primarily by the bandgap of the material, which increases with temperature. Wide-bandgap (WBG) power semiconductors, primarily silicon carbide (SiC) and gallium nitride (GaN), have been adopted for use in these applications, but exhibit a degradation in performance at elevated temperatures. As such, gallium oxide (Ga2O3), an ultrawide-bandgap (UWBG) material with controllable doping and the potential for inexpensive substrates, has presented itself as a potential contender for use in high-temperature power electronics applications. The UWBG of Ga2O3, 4.8 eV compared to 1.1 eV for Si, 3.2 eV for SiC, and 3.4 eV for GaN, allows it to achieve nearly 1033 lower intrinsic carrier concentration than Si, permitting Ga2O3 power devices to theoretically operate at significantly higher temperatures. In addition, unipolar Ga2O3 devices have a better theoretical limit with respect to the relationship between on-resistance and breakdown voltage, which could enable higher power density and power conversion efficiency. While Ga2O3 exhibits potential in these regards, its low thermal conductivity (11–27.0 W/m·K compared to 148 W/m·K for Si, 350 W/m·K for SiC, and 130 W/m·K) means that standard packaging and cooling techniques are not suitable or effective. Furthermore, conventional polymeric and organic encapsulant materials are typically limited to operating temperatures of 200 °C and novel materials must be evaluated. This work outlines and evaluates an electro-thermal device-package co-design modeling platform that can be utilized for the efficient and accurate modeling of Ga2O3 devices and their associated packaging, with the goal of overcoming the challenges of the low thermal conductivity of Ga2O3. This permits for the electrical and thermal performance of the devices and the package to be designed in tandem for an effective design. Next, six high-temperature encapsulation materials are evaluated and conclusions are drawn about each material's feasibility for use as a dielectric encapsulation material for a power module operating at temperatures exceeding 250 °C. This simulation platform and material analysis was then used to design and fabricate a 300 °C, 1.2 kV half-bridge power module utilizing Ga2O3 diodes to assess thermal and electrical performance.
EMI Suppression and Performance Enhancement for Truly Differential Gate Drivers
Miranda-Santos, Jesi (Virginia Tech, 2023-06-30)
The increasing market demand for wideband gap (WBG) power switches has led to heightened competition to increase converter power density, switching frequencies, and reduce form factor, among other factors. However, this technology has also brought about an increase in encounters with electromagnetic interference (EMI), posing significant challenges. Nevertheless, the maturation of power switches has been accompanied by an improvement in gate drive technology aimed at resolving EMI challenges, albeit at a higher component and cost expense. This thesis aims to design, analyze, and implement a recent innovative differential gate driver for a 1.2 kV SiC MOSFET full bridge module. The purpose of this design is to mitigate EMI, improve performance, and reduce the number of filtering elements that are typically required. The investigation into the impact of EMI on electrical systems involves exploring factors such as testing equipment, power supplies, and gate drive layout. Based on these considerations, system and sub-system level analyses are conducted to derive practical design recommendations for implementing the differential gate driver. Three gate drive PCBs are designed and evaluated through extensive double pulse tests (DPTs). Furthermore, continuous switching of the driver presents its own set of challenges that are not apparent during the DPTs, requiring further exploration of low-cost solutions. Finally, a comparison between custom and discrete module solutions employing 1.2 kV SiC MOSFETs is conducted, highlighting the advantages and disadvantages of each approach. The solutions proposed in this work are intended to be extended to other gate drive ICs, with the goal of providing valuable insights and guidelines for EMI suppression and gate driver performance enhancement.
Fabrication Refinements of Advanced Packaging Techniques for Medium-Voltage Wirebond-less Multi-Chip Power Modules
Lester, Danielle Kathryn (Virginia Tech, 2023-06-20)
Three growing power electronics applications have massive requirements for properly operating their medium-voltage and high-voltage systems: electric transportation, renewable energy, and the power grid. Their needs include dense power systems with higher efficiency and higher voltage and current devices. This requires devices with higher switching frequencies to lower the size of the passives in the converter and devices that can withstand higher operating temperatures as components move closer together to improve power densities. Devices that achieve higher switching speeds and lower specific on-state resistances also reduce losses. Wide bandgap devices (WBG) like silicon carbide (SiC) have a higher bandgap, higher electric field strength, higher thermal conductivity, and lower carrier concentration than silicon (Si). This allows for higher temperature operation, faster switching, higher voltage blocking, and lower power losses, directly meeting the requirements of the previously noted applications. However, the current packaging schemes are limiting the ability of SiC to operate in these applications by applying packaging schemes used for Si. Therefore, it is critical to use and refine advanced packaging techniques so that WBG devices can better operate and meet the growing demands of these power electronic applications. Low-inductance, wirebond-less, high-density, scalable modules are possible due to advanced packaging methods. While beneficial to the operation and design, these techniques introduce new challenges to the fabrication process. This requires refinement to improve the yield of sandwich-structure modules with wirebond-less interconnects. For this module, encapsulated, silver-sintered substrates reduce the peak electric field within the package, improving the partial discharge inception voltage to meet insulation requirements. It is essential to have a uniform bondline between the substrates to achieve all bond connections and improve reliability. Silver sintering is also used to attach the molybdenum (Mo) post interconnects. These interconnects allow for sandwich-structure modules with low inductances; however, they have tolerance variation from manufacturing and bondline thicknesses, which become problematic for multi-chip power modules with an increased number of die and posts. The variation results in tilt, causing some posts to disconnect altogether. Additionally, soldering MCPMs involves a large thermal mass that the soldering reflow profile from a datasheet does not account for. Ultimately, these fabrication concerns can result in misalignment or disconnected post interconnects to the top substrate. Post interconnect planarity and alignment are vital for this multi-chip power module to avoid open or shorted connections that can derate switch positions. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver (Ag) sintering is addressed in dried preform and wet paste cases. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules.
Field-Grading in Medium-Voltage Power Modules Using a Nonlinear Resistive Polymer Nanocomposite Coating
Zhang, Zichen (Virginia Tech, 2023-09-07)
Medium-voltage silicon carbide power devices, due to their higher operational temperature, higher blocking voltage, and faster switching speed, promise transformative possibilities for power electronics in grid-tied applications, thereby fostering a more sustainable, resilient, and reliable electric grid. The pursuit of increasing power density, however, escalates the blocking voltage and shrinks the module size, consequently posing unique insulation challenges for the medium voltage power module packaging. The state-of-the-art solutions, such as altering the geometry of the insulated-metal-substrates or thickening or stacking them, exhibit limited efficacy, inflate manufacturing costs, raise reliability concerns, and increase thermal resistance. This dissertation explores a material-based approach that utilizes a nonlinear resistive polymer nanocomposite field-grading coating to enhance insulation performance without compromising thermal performance for medium-voltage power modules. The studied polymer nanocomposite is a mutual effort of this research and NBE Technologies. Instead of using field-grading materials as encapsulation, a thin film coating (about 20 μm) can be achieved by painting the polymer nanocomposite solution to the critical regions to grade the electric field and extend the range of the applicability of the bulk encapsulation. A polymer nanocomposite's electrical properties were characterized and found theoretically and experimentally to be effective in improving the insulation performance or increasing the partial discharge inception voltage, of direct-bonded-copper substrates for medium-voltage power modules. By applying the polymer nanocomposite coating on the direct-bonded- copper triple-point edges, the partial discharge inception voltages of a wide range of direct-bonded-coppers increased by 50-100%. To assure its effectiveness for heated power modules during operation, this field-grading effect was then evaluated at elevated temperatures up to 200°C and found almost unchanged. The nanocomposite's long-term efficacy was further corroborated by voltage endurance tests. Building on these promising characterizations, functional power modules were designed, fabricated, and tested, employing the latest packaging techniques, including double-sided cooling and silver-sintering. Prototypes of 10-kV and 20-kV silicon carbide diode modules confirmed the practicality and efficacy of the polymer nanocomposite. The insulation enhancements observed at the module level mirrored those at the substrate level. Moreover, the polymer nanocomposite coating enabled modules to use insulated-metal-substrates with at least 100% thinner ceramic, resulting in a reduction of at least 30% in the junction-to-case thermal resistance of the module. Subsequently, to test the nanocomposite's performance during fast-switching transients (> 300 V/ns), 15-kV silicon carbide MOSFET modules were designed, fabricated, and evaluated. These more complex modules passed blocking tests, partial discharge tests, and double-pulse tests, further validating the feasibility of the nonlinear resistive polymer nanocomposite field-grading for medium-voltage power modules. In summary, this dissertation presents a comprehensive evaluation of a nonlinear resistive polymer nanocomposite field-grading coating for medium-voltage power modules. The insights and demonstrations provided in this work bring the widespread adoption of this packaging concept for medium-voltage power modules significantly closer to realization.
Hard Switched Robustness of Wide Bandgap Power Semiconductor Devices
Kozak, Joseph Peter (Virginia Tech, 2021-08-30)
As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors.
Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module
Watt, Grace R. (Virginia Tech, 2020-01-22)
This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% difference in V_th had 119.9 µJ more energy loss and was 22.2°C hotter during continuous testing than the most consistently performing balanced module with 0.6% difference inV_th.
Multifaceted Codesign for an Ultra High-Density, Double-Sided Cooled Traction Inverter Half Bridge Module
Roy, Aishworya (Virginia Tech, 2024-01-02)
The automotive sector finds itself undergoing a significant and substantial transformation, propelled by the pronounced proliferation of electric vehicles (EVs) and autonomous driving technologies. As the industry proactively adapts to embrace this, an increasingly pressing demand becomes evident for higher performance, reliability, sustainability, and speed. Semiconductor packages emerge as primary catalysts within this ongoing revolution, positioned squarely at the forefront to assume a critical and indispensable function in facilitating the realization of these fundamental objectives. Commercial vehicle manufacturers are taking steps to respond to these demands for sustainability and speed, the driving force in facilitating this being the shift from Si IGBTs to SiC MOSFETs. Silicon Carbide is an increasingly popular choice in inverter module fabrication for electric vehicle applications owing to its inherent characteristics such as reduced on resistance, higher blocking voltage, and higher temperature stability that enable high power density, increased efficiency, and speeds. This work focuses on developing and fabricating a high-density 1.7 kV, 300 A SiC MOSFET half-bridge power module tailored for a 280-320 kW, 2-level inverter configuration. Co-designed with the busbar and gate driver, the custom power module stresses efficient heat dissipation, minimized parasitic inductance, and a compact footprint. Key target parameters to achieve optimal performance include a Rdson below 20 mΩ, Rthjc under 0.2 K/W and a switching time below 20 ns. The proposed module features a double-sided cooling sandwiched structure, an integrated thermistor for health and degradation monitoring, and incorporates three Wolfspeed 3rd generation 1.7 kV, 18 mΩ devices per switch position. The simulated power loop inductance is 14.5 nH, the simulated parasitic resistance is 0.265 m, and the simulated junction-to-case thermal resistance is 0.12182 ℃/W. To keep the die temperature below 150 ℃, a cooling coefficient of 5500 W/m2 is necessary.
Output Capacitance Loss Measurement and Validation for Low-Voltage Silicon and GaN Devices in DC-DC Converter Applications
Soni, Abhinav (Virginia Tech, 2023-07-14)
With the rise of soft-switched converter topologies which enable high-frequency power conversion, there has been a premise that these converter topologies can help achieve loss-less switching in a power device. However, this theory is not completely true as there even with soft-switching there is some degree of loss associated in the form of output capacitance-related hysteresis loss, channel turn-off loss, and loss during the dead-time period in these converter topologies. The soft-switching converters utilize the existence of the device's output capacitance (COSS), which is charged and discharged consecutively at each switching cycle, and a hysteresis loss exists due to the difference in charging and discharging output capacitance. In order fully utilize the potential of these novel soft-switching topologies, we need to investigate further into the origins of these losses or loss mechanisms, methods to measure or compute these losses, and then devise ways to optimize the loss for a given application. This work focuses on exploring methods to quantify this loss for different operating conditions like device current, switching frequency, dV/dT, etc. In this aspect, some methods have been studied and used to quantify this hysteresis loss for a variety of power devices like SI and GaN. It is reported that only channel turn-off losses exist in devices with ZVS transition, however, we found that the charging and discharging of COSS is not loss-free and thus it is important that we account for this loss in the design process. Finally, the loss data obtained from these tests are compared with each other for five different power devices to validate their applicability, and later these test results are used to get an optimized device selection criterion for the best possible efficiency and minimal losses for a ZVS application.
Reliability Evaluation of Large-Area Sintered Direct Bonded Aluminum Substrates for Medium-Voltage Power Modules
Gersh, Jacob Daniel (Virginia Tech, 2021-06-16)
This thesis investigates techniques for prototyping and evaluation of medium voltage (MV) power module packages. Specific focus will be given to the utilization of silver sintering as a bonding method for high temperature, high density power modules. Nano-silver paste and preform will be examined in detail as enabling technologies for a new generation of power electronics. To accomplish this task, analysis and characterization of the metal-ceramic substrate and its structure is performed. First, finite element models are created to evaluate the fatigue behavior of the large area bonds in the substrate structure. Prototypes of these multi-layer substrates have also been fabricated and will be subjected to thermal cycling tests for experimental verification of the efficacy of their sintered silver bonds. Stacked direct-bonded aluminum (DBA) substrates have been found to withstand up to 1000 thermal cycles of –40 °C to 200 °C when attached with low pressure-assisted silver sintering. The thermal performance of 10 kV SiC power module utilizing multi-layer DBA substrates bonded with a large-area, low pressure-assisted sintered silver bond will also be examined to ensure the sintered bond is viable for the harsh operating conditions of MV modules. A junction-to-case thermal resistance of 0.142 °C/W is measured on a module prototype utilizing stacked DBA substrates. Finally, analysis of a double-sided cooling scheme enabled by large area sintering is simulated and prototyped to demonstrate a 6.5 kV package for a MV power device. Residual stress failures induced by a highly rigid structure have been examined and mitigated through implementation of a 5 MPa pressure-assisted, double-sided silver sintering approach.
Robustness of Gallium Nitride Power Devices
Zhang, Ruizhe (Virginia Tech, 2023-09-05)
Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids.
Thermo-mechanical Analysis of a Custom PCB-DBC Hybrid Package for a (650 V, 150 A) e-GaN HEMT
Nicholas, Carl Peter (Virginia Tech, 2023-05-24)
With the potential to improve upon silicon (Si ) based power electronics exhausted, the push for improvement now lies with wide bandgap (WBG) materials like gallium nitride (GaN). With a larger bandgap, higher electron mobility, and higher electrical field strength than Si, GaN high electron mobility transistors (HEMTs) can have lower on-state losses and higher switching frequencies in a smaller package. This makes GaN HEMTs an attractive choice for compact, high efficiency power devices. However, the package designs used for Si cannot be used for GaN HEMTs, requiring novel, chip-scale designs that are optimized for low electrical parasitics and low thermal resistance. Recent Center for Power Electronics (CPES) research culminated in a printed circuit board-direct bonded copper (PCB-DBC) hybrid package to house a 650 V, 150 A GaN HEMT. Called the PCB-Interposer-on-DBC package, it utilizes a DBC for heat extraction while using vertical pin interconnects to minimize electrical parasitics. Previous work did not investigate the design's locations of expected failure or reliability. With thermally generated mechanical fatigue a consistent cause of electronics failure, it must be investigated for the design to move beyond the prototyping phase. Thermo-mechanical fatigue failure is the brittle fracture of bonds caused by thermally induced warpage. The thermal warpage is the consequence of the bonded package components having a coefficient of expansion (CTE) mismatch while being subjected to temperature changes during operation. Multiphysics simulation software have previously quantified the fatigue placed on bonds exposed to these cyclic conditions, with a common metric being the volume-averaged inelastic strain energy density gained per cycle (ΔWavg). ΔWavg can identify which bonds are subjected to the greatest amount of fatigue and will thus fail first, and then quantify the effect of design alterations on those vulnerable bonds. A common design alteration seen in solder ball packaging is adding a polymeric material that encapsulates the bonds. If the polymer has a CTE like that of the package substrates and an elastic modulus (E) exceeding 1 GPa, it constrains the thermal warpage and lowers bond fatigue. This thesis uses thermo-mechanical simulations to provide evidence on which bonds fail first in the package, and that material-based methods of fatigue reduction used in solder ball packing apply to this novel package. Chapter 1 explains how a desire to reduce the cost and increase the performance of electric vehicles led to the development of the PCB-Interposer-on-DBC design, and that the package's response to thermo-mechanical fatigue is unknown. The concepts of thermo-mechanical fatigue and using encapsulants to reduce it are established, along with how simulations are used to study said fatigue. Chapter 2 serves two purposes, the first being an explanation of the simulation settings and metrics used to establish the quality and assumptions used, and the second being a beginners guide on how to create these simulations. Chapter 3 identifies the most probable locations of initial package failure and identifies what encapsulants minimize ΔWavg on those locations. The sintered silver bond expected to fail first is the Internal Gate bond, and an encapsulant with the maximum possible E and 8 ppm/°C minimizes ΔWavg. The Sn60Pb40 bond expected to fail first is the External Source 4 bond and using an encapsulant with the maximum possible E and a CTE of 24 ppm/°C minimizes ΔWavg. While ΔWavg cannot determine which of the two bonds fails first as they are made of different materials, the Internal Gate is prioritized as it has a higher per-cycle fatigue and to prevent loss of the gate signal. Chapter 4 demonstrates how to perform a brief encapsulant study while ranking the expected cycles to failure when using four different encapsulant options. The first two options are to use no encapsulant or silicone gel. As the elastic modulus of silicone gels are too low to restrict or couple the thermally generated warpage, using silicone gel results in a ΔWavg comparable to using no encapsulant. The rigid encapsulant with the properties most like the optimal encapsulant identified for Internal Gate has the lowest ΔWavg¬ of the encapsulants tested. Guidelines are established for what properties an encapsulant must have to outperform said rigid encapsulant. This work uses simulations to provide evidence that encapsulant methods used in ball grid array (BGA) packaging to reduce fatigue apply to a novel GaN HEMT package. By identifying the first-failure locations of the package, establishing what existing encapsulant should be used, and what encapsulation it should eventually be replaced with, these results provide the groundwork for both experimental temperatures cycling and more complex simulations. Such work fills the gap in understanding the reliable lifetime and common failure mechanisms of the PCB-Interposer-on-DBC package.
Three-Dimensional Loss Effects of a Solenoidal Inductor with Distributed Gaps
Nassar, Rajaie (Virginia Tech, 2024-06-04)
This thesis investigates the disparities in losses between 2D-based design simulations and a 3D realization of solenoidal inductors featuring distributed gaps. The inductor geometry entails a solenoidal copper winding enveloped by sintered ferrite rings and end caps, with the air gap required for energy storage distributed over multiple smaller discrete gaps. The simulated 3D structure possesses higher losses than its 2D cross-section due to inherent structural features. The research culminates in two contributions. First, a practical two-variable design approach is presented, leveraging matrix algebra to succinctly represent the decision quantities as functions of the two most important variables to the application. The procedure results yield several informative plots that assist in selecting a design that meets the efficiency and thermal limits. Second, a detailed explanation is provided on the 3D loss effects, along with the recommended design considerations and a method to estimate the dominant 3D loss effect using simple 2D simulations. The design recommendations address a 26-fold increase in the core loss of the outer ferrite rings. They also reduce the copper loss due to the termination effect by 55% using spacer ferrite layers. A simple 2D simulation method is proposed to accurately predict the increased 3D copper loss due to the axial shift of the winding to within 3% and runs 60 times faster than the equivalent 3D simulation. Additionally, a derived equation for the optimal turn spacing aligns with the simulation results with <6% error, offering practical insights for design optimization. These results enable the design of a low-loss solenoidal inductor and accurate loss estimations without running lengthy and complicated 3D simulations. A 13 µH, 150 Arms solenoidal inductor prototype for operation in a 10 kV-to-400 V, 50 kW converter cell serves as empirical validation, corroborating the efficacy of the proposed analysis and design methodology.

Browsing by Author "Dimarino, Christina Marie"

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