Browsing by Author "Guido, Louis J."

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    Applications in Remote Sensing Using the Method of Ordered Multiple Interactions
    Westin, Benjamin Alexander (Virginia Tech, 2013-04-24)
    The Method of Ordered Multiple Interactions provides a numerical solution to the integral
    equations describing surface scattering which is both computationally efficient and reliably
    convergent. The method has been applied in a variety of ways to solving the electromagnetic
    scattering from perfectly-conducting rough surfaces. A desire to more accurately predict
    the scattering from natural terrain has led to the representation of the surface material as
    penetrable instead of conductive.

    For this purpose, the Method of Ordered Multiple Interactions is applied to numerically
    solve the electromagnetic scattering from randomly-rough dielectric surfaces. A primary
    consequence of the penetrable surface material is the introduction of a pair of coupled integral equations in place of the single integral equation used to solve the problem with a perfectly conducting surface. The method is tested and analyzed by developing independent scattering solutions for canonical cases in a transform domain and by comparing results with solutions from other techniques.

    The dielectric implementation of the Method of Ordered Multiple Interactions is used to solve
    the electromagnetic scattering from a class of randomly-rough dielectric surfaces. This allows
    for the characterization of the effect of a number of transmitter and surface parameters in the
    scattering problem, observing bistatically and also specifically in the backscatter direction.

    MOMI is then applied as a method to examine subsurface penetration characteristics from
    a similar family of rough surfaces. Characteristics of the environment parameters and the
    scattered field itself are examined, and the numerical challenges associated with observing
    beneath the surface are identified and addressed.

    The Method of Ordered Multiple Interactions is then incorporated as a major component of
    a larger solution which computes the total scattering when a dielectric object is buried just
    beneath the rough surface. This hyrid approach uses MOMI and the Method of Moments to
    iteratively account for multiple interactions between the target and the dielectric interface,
    enabling the study of scattering from the combined environment of a rough surface and the
    embedded object, as well as the individual scattering events which combine to form the
    steady-state solution.
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    Applications of Non-linearities in RF MEMS Switches and Resonators
    Vummidi Murali, Krishna Prasad (Virginia Tech, 2015-04-06)
    The 21st century is emerging into an era of wireless ubiquity. To support this trend, the RF (Radio Frequency) front end must be capable of processing a range of wireless signals (cellular phone, data connectivity, broadcast TV, GPS positioning, etc.) spanning a total bandwidth of nearly 6 GHz. This warrants the need for multi-band/multi-mode radio architectures. For such architectures to satisfy the constraints on size, battery life, functionality and cost, the radio front-end must be made reconfigurable. RF-MEMS (RF Micro-Electro-Mechanical Systems) are seen as an enabling technology for such reconfigurable radios. RF-MEMS mainly include micromechanical switches (used in phase shifters, switched capacitor banks, impedance tuners etc.) and micromechanical resonators (used in tunable filters, oscillators, reference clocks etc.). MEMS technology also has the potential to be directly integrated into CMOS (Complementary metal-oxide semiconductor) ICs (Integrated Circuits) leading to further potential reductions of cost and size. However, RF-MEMS face challenges that must be addressed before they can gain widespread commercial acceptance. Relatively low switching speed, power handling, and high-voltage drive are some of the key issues in MEMS switches. Phase noise influenced by non-linearities, need for temperature compensation (especially Si based resonators), large start-up times, and aging are the key issues in Si MEMS Resonators. In this work potential solutions are proposed to address some of these key issues, specifically the reduction of high voltage drives in switches and the reduction of phase noise in MEMS resonators for timing applications. MEMS devices that are electrostatically actuated exhibit significant non-linearities. The origins of the non-linearities are both electrical (electrostatic actuation) and mechanical (dimensions and material properties). The influence of spring non-linearities (cubic and quadratic) on the performance of switches and resonators are studied. Gold electroplated fixed-fixed beams were fabricated to test the phenomenon of dynamic (or resonant) pull-in in shunt switches. The dynamic pull-in phenomenon was also tested on commercially fabricated lateral switches. It is shown that the resonant pull-in technique reduces the overall voltage required to actuate the switch. There is an additional reduction of total actuation voltage possible via applying an AC actuation signal at the correct non-linear resonant frequency. The demonstrated best case savings from operating at the non-linear resonanceis 50 % (for the lateral switch) and 60 % (for the vertical switch) as compared to 25 % and 40 % respectively using a fixed frequency approach. However, the timing response for resonant pull-in has been experimentally shown to be slower than the static actuation. To reduce the switching time, a shifted-frequency method is proposed where the excitation frequency is shifted up or down by a discrete amount 'Ω after a brief hold time. It was theoretically shown that the shifted-frequency method enables a minimum realizable switching time comparable to the static switching time for a given set of actuation frequencies. The influence of VDC on the effective non-linearities of a fixed-fixed beam is also studied. Based on the dimensions of the resonator and the type of resonance there is a certain VDC,Lin where the response is near linear (S ' 0). In the near-linear domain, the dynamic pull-in is the only upper bound to the amplitude of vibrations, and hence the amplitude of output current, thereby maximizing the power handling capacity of the resonator. Apart from maximizing the output current, it is essential to reduce the amplitude and phase variations of the displacement response which are due to noise mixing into frequency of interest, and are eventually manifested as output phase noise due to capacitive current nonlinearity. Two major aliasing schemes were analyzed and it was shown that the capacitive force non-linearity is the major source of mixing that causes the up-conversion of 1/f frequency into signal sidebands. The resonator's periodic response (displacement) is defined by a set of two first- order nonlinear ordinary differential equations that describe the modulation of amplitude and phase of the response. Frequency response curves of amplitude and frequency are determined from these modulation equations. The zero slope point on the amplitude resonance curve is the peak of the resonance curve where the phase ('dc) of the response is ±π/2. For a strongly non-linear system, the resonance curves are skewed based on the amount of total non-linearity S. For systems that are strongly non-linear, the best region to operate the resonator is the fixed point that correspond to infinite slope ('dc = ±2π/3) in the frequency response of the system. The best case phase noise response was analytically developed for such a fixed point. Theoretically at this fixed point, phase noise will have contributions only from 1/f noise and not from 1/f2 and 1/f3. The resonators phase can be set by controlling the rest of the phase in the loop such that the total phase around the loop is zero or 2π. In addition, this work has also developed an analytical model for a lateral MEMS switch fabricated in a commercial foundry that has the potential to be processed as MEMS on CMOS. This model accounts for trapezoidal cross sections of the electrodes and springs and also models electrostatic fringing as a function of the moving gap. The analytical model matches closely with the Finite Element (FEA) model.
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    Comparison and Design of High Efficiency Microinverters for Photovoltaic Applications
    Dominic, Jason (Virginia Tech, 2014-11-14)
    With the decrease in availability of non-renewable energy sources coupled with the increase in the amount of energy required for the operation of personal electronic devices there has been an increased focus on developing systems that take advantage of renewable energy sources. Renewal energy sources such as photovoltaic (PV) panels have become more popular due to recent developments in PV panel manufacturing that decreases material costs and improves energy harvesting efficiency. Since PV sources are DC sources power conversion stages have to be used in order to interface this power to the existing electrical utility system. The structure of large scale PV systems usually consists of several PV panels connected in series to achieve a high input source voltage that can be fed into a high power centralized DC-AC inverter. The drawback to this approach is that when the PV panels are subjected to less than ideal conditions. If a single PV panel is subjected to drastically less solar irradiation during cloud conditions, then its output power will drop dramatically. Since this panel is series connected with the other PV panels, their current output is also dragged low decreasing the power output of the system. Algorithms that have the power converter operate at different input conditions allow the system to operate at a maximum power point (MPP), however this only allows the system to operate at a higher power point and not the true MPP. To get around this limitation a new PV system implementation was created by giving each panel its own DC-AC power conversion system. This configuration gives each panel the ability to operate at its own MPP increasing the total system energy harvest. Another advantage of the single panel DC-AC microinverter power conversion stage is that the outputs are parallel connected to the utility grid easily allowing the ability to expand the system without having to shut down the entire system. The most prevalent implementation of the microinverter consists of a single power converter that uses the PV low voltage DC and outputs high voltage AC. In order to ensure that the double line AC ripple does not propagate to the PV panel a large bank of electrolytic capacitors are used to buffer the ripple. There is concern that the electrolytic capacitor will degrade over time and affect the system efficiency. To get around having to use electrolytic capacitors a two stage microinverter has been proposed. The two stage microinverter consists of a DC-DC converter that steps up the low DC voltage of the PV panel to high voltage DC and the second stage is a DC-AC inverter that takes the high voltage DC and converts it to high voltage AC. There is a capacitor that connects the two power converter stages called the DC link capacitor which can buffer the double line energy ripple without using electrolytic capacitors. This thesis focuses on the review of several DC-AC inverter topologies suitable for use in PV microinverter systems. Operation capabilities such as common mode noise and efficiency are compared. The main focus of the review is to determine the optimal DC-AC inverter using the performance metrics of cost, efficiency and common mode performance. A 250 W prototype is built for each inverter topology to verify its performance and operation.
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    Connection between Carbon Incorporation and Growth Rate for GaN Epitaxial Layers Prepared by OMVPE
    Ciarkowski, Timothy; Allen, Noah P.; Carlson, Eric; McCarthy, Robert; Youtsey, Chris; Wang, Jingshan; Fay, Patrick; Xie, Jinqiao; Guido, Louis J. (MDPI, 2019-08-01)
    Carbon, a compensator in GaN, is an inherent part of the organometallic vapor phase epitaxy (OMVPE) environment due to the use of organometallic sources. In this study, the impact of growth conditions are explored on the incorporation of carbon in GaN prepared via OMVPE on pseudo-bulk GaN wafers (in several cases, identical growths were performed on GaN-on-Al2O3 templates for comparison purposes). Growth conditions with different growth efficiencies but identical ammonia molar flows, when normalized for growth rate, resulted in identical carbon incorporation. It is concluded that only trimethylgallium which contributes to growth of the GaN layer contributes to carbon incorporation. Carbon incorporation was found to decrease proportionally with increasing ammonia molar flow, when normalized for growth rate. Ammonia molar flow divided by growth rate is proposed as a reactor independent predictor of carbon incorporation as opposed to the often-reported input V/III ratio. A low carbon concentration of 7.3 × 1014 atoms/cm3 (prepared at a growth rate of 0.57 µm/h) was obtained by optimizing growth conditions for GaN grown on pseudo-bulk GaN substrates.
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    Dependence of Set, Reset and Breakdown Voltages of a MIM Resistive Memory Device on the Input Voltage Waveform
    Ghosh, Gargi (Virginia Tech, 2015-05-27)
    Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one of the prime candidates to supplant current Nonvolatile Memory (NVM) based on the floating gate (FG) MOSFET transistor, which is at the end of its scaling capability. The RRAM technology comprises two subcategories: 1) the resistive phase change memory (PCM), which has been very recently deployed commercially, and 2) the filamentary conductive bridge RAM (CBRAM) which holds the promise of even better scaling potential, less power consumption, and faster access times. This thesis focuses on several aspects of the CBRAM technology. CBRAM devices are based on nanoionics transport and chemo-physical reactions to create filamentary conductive paths across a dielectric sandwiched between two metal electrodes. These nano-size filaments can be formed and ruptured reliably and repeatedly by application of appropriate voltages. Although, there exists a large body of literature on this topic, many aspects of the CBRAM mechanisms and are still poorly understood. In the next paragraph, the aspects of CBRAM studied in this thesis are spelled out in more detail. CBRAM cell is not only an attractive candidate for a memory cell but is also a good implementation of a new circuit element, called memristor, as postulated by Leon Chua. Basically, a memristor, is a resistor with a memory. Such an element holds the promise to mimic neurological switching of neuron and synapses in human brain that are much more efficient than the Neuman computer architecture with its current CMOS logic technology. A memristive circuitry can possibly lead to much more powerful neural computers in the future. In the course of the research undertaken in this thesis, many memristive properties of the resistive cells have been found and used in models to describe the behavior of the resistive switching devices. The research performed in this study has also an immediate commercial application. Currently, the semiconductor industry is faced with so-called latency scaling dilemma. In the past, the bottleneck for the signal propagation was the time delay of the transistor. Today, the transistors became so fast that the bottleneck for the signal propagation is now the RC time delay of the interconnecting metal lines. Scaling drives both, resistance and parasitic capacitance of the metal lines to very high values. In this context, one observes that resistive switching memory does not require a Si substrate. It is therefore an excellent candidate for its implementation as an o n-chip memory above the logic circuits in the CMOS back-end, thus making the signal paths between logic and memory extremely short. In the framework of a Semiconductor Research Corporation (SRC) project with Intel Corporation, this thesis investigated the breakdown and resistive switching properties of currently deployed low k interlayer dielectrics to understand the mechanisms and potential of different material choices for a realization of an RRAM memory to be implemented in the back-end of a CMOS process flow.
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    Design and Analyses of a Dimple Array Interconnect Technique for Power Electronics Packaging
    Wen, Sihua (Virginia Tech, 2002-08-02)
    This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint.
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    Design and Analysis of Whispering Gallery Mode Semiconductor Lasers
    Hajjiah, Ali T. (Virginia Tech, 2009-01-19)
    Significant technical barriers currently prevent the wide spread adoption of WGM lasers as building blocks in large-scale photonic integrated circuits. The first challenge is to reduce the electrical power consumption at desirable levels of light output power. The second target is to obtain directional light emission without sacrificing other laser performance metrics. The best opportunity for success lies in the pursuit of small micro-Pillar lasers with spiral-geometry cavities. Process technology has been demonstrated for making high-performance WGM lasers including a refined ICP etching process for fabricating micro-Pillar cavities with sidewall roughness less than 10 nm and a new hydrogenation based approach to achieving current blocking that is compatible with all other processing steps and robust in comparison with earlier reports. A comprehensive photo-mask has been designed that enables investigation of the interplay between device geometry and WGM laser performance. Emphasis has been placed on enabling experiments to determining the impact of diffraction and scattering losses, current and carrier confinement, and surface recombination on electrical/optical device characteristics. In addition, a methodology has been developed for separating out process optimization work from the task of identifying the best means for directional light out-coupling. Our device fabrication methods can be proven on WGM lasers with pure cylindrical symmetry, hence results from these experiments should be independent of any specific light output coupling scheme. Particular attention has been paid to the fact that device geometries that give the best performance for purely symmetrical cavities may not yield the highest level of light emission from the spiral output notch. Such considerations seem to be missing from much of the earlier work reported in the literature. Finally, our processing techniques and device designs have resulted in individual WGM lasers that outperform those made by competitors. These devices have been incorporated into multi-element, coupled-cavity optical circuits thereby laying the groundwork for construction of digital photonic gates that execute AND, OR, and NOT logic functions.
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    Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen
    Dimarino, Christina Marie (Virginia Tech, 2019-01-03)
    Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.
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    Design Methodology and Materials for Additive Manufacturing of Magnetic Components
    Yan, Yi (Virginia Tech, 2017-04-11)
    Magnetic components such as inductors and transformers are generally the largest circuit elements in switch-mode power systems for controlling and processing electrical energy. To meet the demands of higher conversion efficiency and power density, there is a growing need to simplify the process of fabricating magnetics for better integration with other power electronics components. The potential benefits of additive manufacturing (AM), or more commonly known as three-dimensional (3D) printing technologies, include shorter lead times, mass customization, reduced parts count, more complex shapes, less material waste, and lower life-cycle energy usage—all of which are needed for manufacturing power magnetics. In this work, an AM technology for fabricating and integrating magnetic components, including the design of manufacturing methodology and the development of the feedstock material, was investigated. A process flow chart of additive manufacturing functional multi-material parts was developed and applied for the fabrication of magnetic components. One of the barriers preventing the application of 3D-printing in power magnetics manufacturing is the lack of compatible and efficient magnetic materials for the printer's feedstock. In this work, several magnetic-filled-benzocyclobutene (BCB) pastes curable below 250 degree C were formulated for a commercial multi-material extrusion-based 3D-printer to form the core part. Two magnetic fillers were used: round-shaped particles of permalloy, and flake-shaped particles of Metglas 2750M. To guide the formulation, 3D finite-element models of the composite, consisting of periodic unit cells of magnetic particles and flakes in the polymer-matrix, was constructed. Ansoft Maxwell was used to simulate magnetic properties of the composite. Based on the simulation results, the pastes consisted of 10 wt% of BCB and 90 wt% of magnetic fillers—the latter containing varying amounts of Metglas from 0 to 12.5 wt%. All the pastes displayed shear thinning behavior and were shown to be compatible with the AM platform. However, the viscoelastic behavior of the pastes did not exhibit solid-like behavior, instead requiring layer-by-layer drying to form a thick structure during printing. The key properties of the cured magnetic pastes were characterized. For example, bulk DC electrical resistivity approached 107 Ω⋅cm, and the relative permeability increased with Metglas addition, reaching a value of 26 at 12.5 wt%. However, the core loss data at 1 MHz and 5 MHz showed that the addition of Metglas flakes also increased core loss density. To demonstrate the feasibility of fabricating magnetic components via 3D-printing, several inductors of differing structural complexities (planar, toroid, and constant-flux inductors) were designed. An AM process for fabricating magnetic components by using as-prepared magnetic paste and a commercial nanosilver paste was developed and optimized. The properties of as-fabricated magnetic components, including inductance and DC winding resistance, were characterized to prove the feasibility of fabricating magnetic components via 3D-printing. The microstructures of the 3D-printed magnetic components were characterized by Scanning-electron-microscope (SEM). Results indicate that both the winding and core magnetic properties could be improved by adjusting the formulation and flow characteristics of the feed paste, by fine-tuning printer parameters (e.g., motor speed, extrusion rate, and nozzle size), and by updating the curing profile in the post-process. The main contributions of this study are listed below: 1. Developed a process flow chart for additive manufacturing of functional multi-material components. This methodology can be used as a general reference in any other research area targeting the utilization of AM technology. 2. Designed, formulated and characterized low-temperature curable magnetic pastes. The pastes are physically compatible with the additive manufacturing platform and have applications in the area of power electronics integration. 3. Provided an enhanced understanding of the core-loss mechanisms of soft magnetic materials and soft magnetic composites at high frequency applications.
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    Design, Analysis and Experimental Verification of a Mechanically Compliant Interface for Fabricating Reliable, Double-Side Cooled, High Temperature, Sintered Silver Interconnected Power Modules
    Berry, David W. (Virginia Tech, 2014-09-08)
    This research developed a double-side power electronics packaging scheme for high temperature applications exemplified by 1200 V, 150 A silicon devices. The power modules, based on both quarter and half-bridge topologies, were assembled using sintered silver device attachment rather than conventional solder alloys. Thermomechanical stresses in the double-side architecture were mitigated with a compliant layer fabricated from elliptical silver tubes. This research presents an introduction to conventional packaging techniques and their weaknesses. These shortcomings provide the basis for a module design which improves upon module thermal management while also addressing electrical and reliability requirements. The optimum package design enhances heat dissipation with the addition of a substrate bonded to the top electrical pads of the semiconductor devices. The use of sintered silver also increases the useful application temperature by avoiding the creep failure mechanisms of solder alloys. The modules were characterized extensively to quantify thermal and electrical performance. In the case of thermal characterization, the double-side architecture required multiple testing configurations to fully understand the parallel heat flow paths. These results were compared to models constructed using finite element analysis (FEA). The FEA models were also utilized for measurement of strains in multiple package designs to better determine the effects of increased compliance on the relative package cycling lifetime. These lifetimes were then assessed, in part, using experimental passive and cycling tests on functional double-side packages. The resulting power modules exhibited significant decreases in thermal resistance when they are cooled, as designed, from both sides of the module. Even single sided cooling options reveal significant advantages and transient thermal impedance was found to be significantly lower. Power module models revealed the compliant layer was successful in reducing the device shear stresses which was experimentally validated through the use of DC power stage testing. It was found, through double pulse testing and electrical modeling, that parasitic inductances were reduced by utilizing planar bonding and planar symmetrical traces. Finally, modeling of the double-side package with added tube compliance revealed a decrease in plastic and shear strains when compared to other single and double-side package designs. This reduction directly translates to increased cycling lifetime using well known strain based fatigue models.
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    Design, Fabrication and Characterization of a GaAs/InxGa1-xAs/GaAs Heterojunction Bipolar Transistor
    Lidsky, David (Virginia Tech, 2014-10-16)
    Designs for PnP GaAs/InxGa1-xAs/GaAs heterojunction bipolar transistors (HBTs) are proposed and simulated with the aid of commercial software. Band diagrams, Gummel plots and common emitter characteristics are shown for the specific case of x=1, x=0.7, and x linearly graded from 0.75 to 0.7. Of the three designs, it is found that the linearly graded case has the lowest leakage current and the highest current gain. IV curves for all four possible classes of InAs/GaAs heterojunction (nN, nP, pN, pP) are calculated. A pN heterojunction is fabricated and characterized. In spite of the 7% lattice mismatch between InAs and GaAs, the diode has an ideality factor of 1.26 over three decades in the forward direction. In the reverse direction, the leakage current grows exponentially with the magnitude of the bias, and shows an effective ideality factor of 3.17, in stark disagreement with simulation. IV curves are taken over a temperature range of 105 K to 405 and activation energies are extracted. For benchmarking the device processing and the characterization apparatus, a conventional GaAs homojunction diode was fabricated and characterized, showing current rectification ratio of 109 between plus one volt and minus one volt. Because the PnP material for the optimal HBT design was not available, an Npn GaAs/InAs/InAs HBT structure was processed, characterized, and analyzed. The Npn device fails in both theory and in practice; however, by making a real structure, valuable lessons were learned for crystal growth, mask design, processing, and metal contacts.
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    Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices
    Collins, Gustina B. (Virginia Tech, 2006-06-05)
    A low-cost, low-temperature packaging concept is proposed for localized sealing and control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro- Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices require application specific packaging to facilitate their integration, provide protection from the environment, and control interactions with other circuitry. In order to integrate these devices into standard integrated circuit (IC) process flows and minimize damage due to post-fabrication steps, packaging is performed at the wafer level. In this work Indium and Silver are used to seal a monolithic localized hermetic pack- age. The cavity protecting the device is formed using standard lithography-based processing techniques. Metal walls are built up from the substrate and encapsulated by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a predefined RF microsystem. The bond for the seal is then formed by rapid alloying of Indium and Silver using a temperature greater than that of the melting point of Indium. This ensures that the seal formed can subsequently function at temperatures higher than the melting temperature of pure Indium. This method offers a low-temperature bonding technique with thermal robustness suitable for wafer-level process integration. The ultimate goal is to create a seal in a vacuum environment. In this dissertation, design trade-offs made in wafer-level packaging are explained using thermo-mechanical stress and electrical performance simulations. Prototype passive microwave circuits are packaged using the developed packaging process and the performance of the fabricated circuits before and after packaging is analyzed. The effect of the package on coplanar waveguide structures are characterized by measuring scattering parameters and models are developed as a design tool for wafer-level package integration. The small scale of the localized package is expected to provide greater reliability over conventional full chip packages.
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    Development of Bi-Directional Module using Wafer-Bonded Chips
    Kim, Woochan (Virginia Tech, 2015-01-06)
    Double-sided module exhibits electrical and thermal characteristics that are superior to wire-bonded counterpart. Such structure, however, induces more than twice the thermo-mechanical stress in a single-layer structure. Compressive posts have been developed and integrated into the double-sided module to reduce the stress to a level acceptable by silicon dice. For a 14 mm x 21 mm module carrying 6.6 mm x 6.6 mm die, finite-element simulation suggested an optimal design having four posts located 1 mm from the die; the z-direction stress at the chip was reduced from 17 MPa to 0.6 MPa.
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    Development of Low-power Wireless Sensor Nodes based on Assembled Nanowire Devices
    Narayanan, Arvind (Virginia Tech, 2000-07-24)
    Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized.
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    Development of Nanoelectromechanical Resonators for RFIC Applications
    Barnhart, William David (Virginia Tech, 2002-06-14)
    Over the past decade there has been an explosion in the demand for wireless mobile personal communications systems (PCS), a trend that shows no signs of slowing down in the foreseeable future. This demand has created a greater need for low-cost, low-power, compact system solutions. As a result, "single-chip" implementations of wireless functions have received a significant amount of attention. A significant roadblock to complete integration of these functions is the requirement for high-Q resonators in RF filter and tank circuits. Current on-chip techniques being used to realize monolithic RF resonators based on planar inductors, capacitors and active circuits are accompanied by problems such as high loss, large chip area and high power consumption. An alternative to these on-chip solutions is the use of monolithically integrated electromechanical devices. This thesis describes the modeling, fabrication and characterization of nanoelectromechanical (NEM) single crystal silicon resonators. The potential advantages associated with these devices are high-Q, small die area and low power consumption. The development of such devices compatible with modern integrated circuit fabrication techniques offers the possibility for integration of high performance RF filters and resonators onto a single RFIC chip. The advantageous characteristics of these resonators could lead to mobile PCS devices with lower cost and increased battery life. The NEM resonator designs investigated in this work are fabricated using an electron-beam lithography based surface machining process in silicon-on-insulator technology. Various design, fabrication and testing issues are discussed. The feasibility of lateral capacitive actuation and detection in such structures is examined.
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    Die-Attachment on Copper by Nanosilver Sintering: Processing, Characterization and Reliability
    Zheng, Hanguang (Virginia Tech, 2015-04-29)
    Die-attachment, as the first level of electronics packaging, plays a key role for the overall performance of the power electronics packages. Nanosilver sintering has becoming an emerging solder-free, environmental friendly die-attach technology. Researchers have demonstrated the feasibility of die-attachment on silver (Ag) or gold (Au) surfaces by pressure-less or low-pressure (< 5 MPa) nanosilver sintering. This study extended the application of nanosilver sintering die-attach technique to copper (Cu) surface. The main challenge of nanosilver sintering on Cu is the formation of thick Cu oxide during processing, which may lead to weak joints. In this study, different processes were developed based on the die size: for small-area dice (< 5 * 5 mm2), different sintering atmospheres (e.g. forming gas) were applied to protect Cu surface from oxidation; for large-area dice (> 5 * 5 mm2), a double-print, low-pressure (< 5 MPa) assisted sintering process was developed. For both processes, die-shear tests demonstrated die-shear strength can reach 40 MPa. The effects of different sintering parameters of the processing were analyzed by different material characterization techniques. With forming gas as sintering atmosphere, not only Cu surface was protected from oxidation, but also the organics in the paste were degraded with nanosilver particles as catalyst. External pressure applied in the processing not only increased the density of sintered Ag, but also enhanced the contact area of sintered-Ag/Cu interface. Microstructure of Ag/Cu interface were characterized by transmission electron microscopy (TEM). Characterization results indicate that Ag/Cu metallic bonds formed at the interface, which verified the high die-shear strength of the die-attachment. Thermal performance of nanosilver sintered die-attachment on Cu was evaluated. A system was designed and constructed for measuring both transient thermal impedance (Zth) and steady-state thermal resistance (Rth) of insulated gate bipolar transistor (IGBT) packages. The coefficient of variation (CV) of Zth measurement by the system was lower than 0.5%. Lead-free solder (SAC305) was applied in comparison of thermal performance with nanosilver paste. With same sample geometry and heating power level, nanosilver sintered joints on Cu showed in average 12.6% lower Zth and 20.1% lower Rth than SAC305 soldered joints. Great thermal performances of nanosilver sintering die-attachment on Cu were mainly due to the low thermal resistivity of sintered-Ag and the good bonding quality. Both passive temperature cycling and active power cycling tests were conducted to evaluate the reliability of nanosilver sintered joints on Cu. For passive temperature cycling tests (-40 - 125 C), the die-shear strengths of mechanical samples had no significant drop over 1000 cycles, and nanosilver sintered IGBT on Cu packages showed almost no change on Zth after 800 cycles. For active power cycling test (Tj = 45 - 175 C), nanosilver sintered IGBT on Cu assembly had a lifetime over 48,000 cycles. The failure point of the assembly was the detachment of the wirebonds. Great reliability performances of nanosilver sintered die-attachment on Cu were mainly due to the low mismatch of coefficient of thermal expansion (CTE) between sintered-Ag and Cu. Meanwhile, low inter-diffusion rate between Ag and Cu prevented the interface from the reliability issue related to Kirkendall voids, which often took place in tin (Sn) -based solder joints.
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    Effect of Out-Tunneling Leakage and Electron-Hole Asymmetry on Modulation Response of Semiconductor Double Tunneling-Injection Quantum Dot Lasers
    Kar, Saurav (Virginia Tech, 2017-08-03)
    In this thesis, our primary objective was to theoretically analyze the real world modulation bandwidth of a DTI QD laser and this was done by analyzing the effect of out-tunneling leakage of carriers from QDs, and by analyzing the effect of electron-hole asymmetry on the device characteristics. We are confronted with the following results: 1) Effect of Out-Tunneling Leakage on Modulation Bandwidth in Double Tunneling Injection Quantum Dot Lasers To purely focus on this effect, the conditions of instantaneous carrier exchange between the OCL and QW (on each side of the structure) and tunneling injection into QDs are assumed and closed-form analytical expressions for modulation bandwidth are obtained. The relative decrease in modulation bandwidth, due to this effect, in a DTI QD laser (from plots of modulation bandwidth vs j on increasing wout) is then shown to be small, and at ranges of injection currents of operational interest, nearly negligible. Consequently, it is shown that the DTI laser is a robust device in terms of sensitivity to out-tunneling leakage i.e. much effort need not be paid in suppressing this phenomenon. 2) Effect of Electron-Hole Asymmetry on Modulation Bandwidth of Double Tunneling Injection Quantum Dot Lasers On analyzing the effect of electron-hole asymmetry on the device characteristics of a DTI QD laser, it can be noted (from plots of modulation bandwidth vs injection current) that there is no reduction in the maximum modulation bandwidth i.e. electron-hole asymmetry does not indicate a reduction in the effectiveness of such a DTI design. This is shown to occur as the maximum modulation bandwidth depends on both, the effective differential non-stimulated recombination time as well the photon lifetime in the optical cavity. The photon lifetime being much smaller than the former acts as the dominating factor, and hence we see no appreciable change in the maximum modulation bandwidth. In the course of this analysis, we also see that the actual condition i.e. that of electron hole asymmetry is closer, among the cases of symmetry, to symmetry assuming hole parameters rather than electron parameters. As such, in cases where electron-hole symmetry must be used (in order to facilitate numerical simplifications), a recommendation of this study is to use hole parameters instead.
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    Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints
    Jiang, Li (Virginia Tech, 2013-10-17)
    Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic packaging, such as high melting temperature, high electrical/thermal conductivity, and excellent mechanical reliability. It should be noted, however, that pressure (usually between three to five MPa) was added during the sintering stage for attaching power chips with area larger than 100 mm2. This extra pressure increased the complexity of the sintering process. The maximum chip size processed by pressure-free sintering, in the published resources, was 6 x 6 mm2. One objective of this work was to achieve chip-attachment with area of 13.5 x 13.5 mm2 (a chip size of one kind of commercial IGBT) by pressure-free sintering of nano-silver paste. Another objective was to fabricate high-power (1200 V and 150 A) multi-chip module by pressure-free sintering. In each module (half-bridge), two IGBT dies (13.5 x 13.5 mm2) and two diode dies (10 x 10 mm2) were attached to a DBC substrate. Modules with solder joints (SN100C) and pressure-sintered silver joints were also fabricated as the control group. The peak temperature in the process of of pressure-free sintering of silver was around 260oC, whereas 270oC for vacuum reflowing of solder, and 280oC under three MPa for pressure-sintering of silver. The process for wire bonding, lead-frame attachment, and thermocouple attachment are also recorded. Modules with the above three kinds of joints were first characterized by electrical methods. All of them could block 1200 V DC voltage after packaging, which is the voltage rating of bare dies. Modules were also tested up to the rated current (150 A) and half of the rated voltage (600 V), which were the test conditions in the datasheet for commercial modules with the same voltage and current ratings. I-V characteristics of packaged devices were similar (on-resistance less than 0.5 mohm). All switching waveforms at transient stage (both turn-on and turn-off) were clean. Six switching parameters (turn-on delay, rise time, turn-off delay, fall time, turn-on loss, and turn-off loss) were measured, which were also similar (<9%) among different kinds of modules. The results from electrical characterizations showed that both static characterizations and double-pulse test cannot be used for evaluating the differences among chip-attach layers. All modules were also characterized by their thermal performances. Transient thermal impedances were measured by gate-emitter signals. Two setups for thermal impedance measurement were used. In one setup, the bottoms of modules were left in the air, and in the other setup, bottoms of modules were attached to a chiller (liquid cooling and temperature controlled at 25oC) with thermal grease. Thermal impedances of three kinds of modules still increased after 40 seconds for the testing without chiller, since the thermal resistance of heat convection from bottom copper to the air was included , which was much larger than the sum of the previous layers (from IGBT junction, through the chip-attach layer, to the bottom of DBC substrate). In contrast, thermal impedances became almost stable (less than 3%) after 15 seconds for all modules when the chiller was used. Among these three kinds of modules, the module with pressure sintered joints had the lowest thermal impedance and the thermal resistance (tested with the chiller) around 0.609oK/W, In contrast, the thermal resistance was around 964oK /W for the soldered module, and 2.30oK /W for pressure-free sintered module. In summary, pressure-free large-area sintered joints were achieved and passed the fabrication process for IGBT half-bridge module with wiring bonding. Packaged devices with these kinds of joints were verified with good electrical performance. However, thermal performances of pressure-free joints were worse than solder joints and pressure-sintered joints.
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    Electrical Characterization of Gallium Nitride Drift Layers and Schottky Diodes
    Allen, Noah P. (Virginia Tech, 2019-10-09)
    Interest in wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and diamond has increased due to their ability to deliver high power, high switching frequency and low loss electronic devices for power conversion applications. To meet these requirements, semiconductor material defects, introduced during growth and fabrication, must be minimized. Otherwise, theoretical limits of operation cannot be achieved. In this dissertation, the non-ideal current- voltage (IV) behavior of GaN-based Schottky diodes is discussed first. Here, a new model is developed to explain better the temperature dependent performance typically associated with a multi-Gaussian distribution of barrier heights at the metal-semiconductor interface [Section 3.1]. Application of this model gives researches a means of understanding not only the effective barrier distribution at the MS interface but also its voltage dependence. With this information, the consequence that material growth and device fabrication methods have on the electrical characteristics can be better understood. To show its applicability, the new model is applied to Ru/GaN Schottky diodes annealed at increasing temperature under normal laboratory air, revealing that the origin of excess reverse leakage current is attributed to the low-side inhomogeneous barrier distribution tail [Section 3.2]. Secondly, challenges encountered during MOCVD growth of low-doped GaN drift layers for high-voltage operation are discussed with focus given to ongoing research characterizing deep-level defect incorporation by deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) [Section 3.3 and 3.4]. It is shown that simply increasing TMGa so that high growth rates (>4 µm/hr) can be achieved will cause the free carrier concentration and the electron mobilities in grown drift layers to decrease. Upon examination of the deep-level defect concentrations, it is found that this is likely caused by an increase in 4 deep level defects states located at E C - 2.30, 2.70, 2.90 and 3.20 eV. Finally, samples where the ammonia molar flow rate is increased while ensuring growth rate is kept at 2 µm/hr, the concentrations of the deep levels located at 0.62, 2.60, and 2.82 eV below the conduction band can be effectively lowered. This accomplishment marks an exciting new means by which the intrinsic impurity concentration in MOCVD-grown GaN films can be reduced so that >20 kV capable devices could be achieved.
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    Electrical characterization of RuOx/n-GaN Schottky diodes formed by oxidizing ruthenium thin-films in normal laboratory air
    Allen, Noah P.; Ciarkowski, Timothy; Carlson, Eric; Chakraborty, Amrita; Guido, Louis J. (2020-01)
    Schottky diodes were formed by oxidizing Ru thin films deposited on n-type GaN at 400, 500, and 600 degrees C in normal laboratory air, and their electrical behavior was compared to that of a Ru/n-GaN reference device. The GaN epitaxial layers were grown via metalorganic chemical vapor deposition. The ruthenium films were deposited by electron beam evaporation. The Schottky barriers were characterized via current vs voltage (IV) and deep-level transient spectroscopy (DLTS) measurements between 70 and 400 K. The temperature dependent forward bias IV characteristics were fit, and the extracted temperature dependence of the effective barrier height for each device was shown to be caused by inhomogeneity at the metal/semiconductor interface. It was found that barrier inhomogeneity could be well described by a modified log-normal distribution. In reverse bias, it was shown that the low-energy tail of the barrier distribution is an important factor in determining leakage current. Favorable results occur for diodes oxidized at 400 and 500 degrees C, but raising the oxidation temperature to 600 degrees C results in a drastic increase in leakage current. DLTS measurements reveal one electron trap at E-C - 0.57 eV in each of the samples. It was found that the concentration of this 0.57 eV trap increases substantially at 600 degrees C and that trap-assisted tunneling likely contributes an additional pathway for reverse leakage current. (c) 2020 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).