Browsing by Author "Walling, Jeffrey S."

Now showing 1 - 4 of 4
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    Battery Cell Monitoring Unit
    Danson, Eric C. (Virginia Tech, 2023-04-12)
    The proposed cell monitoring unit for sensing voltage, current, and temperature in a 12-cell 18650 lithium-ion battery module aims to be low-power, serving as the core of an energy-efficient battery management system and facilitating battery management functions with cell data. Notable features include a switchable voltage divider, a single op-amp differential amplifier and level shifter, and a high-precision composite amplifier. The proposed circuit is implemented on a printed circuit board. Measurement results show that the highest power dissipation under continuous operation is from the current sensing circuit at 6.03 mW under a 4 A string current, followed by the voltage sensing at 2.52 mW for the top cell and the temperature sensing at 34.9 μW. The measured power figures include the power dissipation from the battery cells in addition to the cell monitoring unit. The maximum output error is 68 mV for cell voltages up to 44.4 V, 36 mA for current up to 4 A, and 0.37 ◦C for temperature up to 73 ◦C.
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    An Edge-Combining Frequency-Multiplying Class-D Power Amplifier
    Nguyen, Hieu Minh; Zhang, Feifei; O'Connell, Ivan; Staszewski, R. Bogdan; Walling, Jeffrey S. (IEEE, 2022-01)
    The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65 nm CMOS prototype achieves output power and system efficiency of 22.3 dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.
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    The Future of Computing: An Energy-Efficient In-Memory Computing Architectures with Emerging VGSOT MRAM Technology
    Sarkar, Md Rubel (Virginia Tech, 2024-04-19)
    This thesis work presents an unique architecture with a capacity of 1.57-Mb storage including in-memory compuitng capability, leveraging state-of-the-art gate voltage assisted spin-orbit torque (VGSOT) magnetic random-access memory (MRAM) technology. Beyond its role as a non-volatile storage solution, this architecture facilitates a diverse array of In-Memory Computing (IMC) operations, inclusive of logic-inside-memory (LinM/LiM), in-memory-dot- product multiplication tailored for binary-neural-networks, and content-accessable memory (CAM). Our designed bit-cell proposed in this architecture occupies a compact area of 0.195 μm2 and exhibits remarkable performance metrics. It achieves impressive writing speeds of 200 MHz and reading speeds of 1.5 GHz, applicable to non-volatile storage tasks and LinM operations. Notably, the LinM functionality supports a wide range of logical operations such as AND, NAND, OR, NOR, and MAJ, while the CAM feature enables efficient data searches of up to 1024 bits. Furthermore, in performance evaluations conducted using the MNIST and FMNIST datasets with a BNN model structured as 512-512-10 (input layer - hidden layer - output layer), the proposed VGSOT MRAM demonstrates exceptional inference accuracy. Specifically, it achieves a high accuracy rate of 97.40% for the MNIST dataset and 84.15% for the FMNIST dataset. In comparison to the 2T1R SOT-MRAM technology, the proposed VGSOT MRAM showcases significant advancements in read performance and reliability metrics. Notably, it features a 65.74% reduction in bit-cell area, alongside 84.78% and 33.4% lower read-write power consumption and 54.11% and 30.57% reduced LinM power consumption, respectively.
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    Multiphase Interpolating Digital Power Amplifiers for TX Beamforming
    Bai, Zhidong; Yuan, Wen; Azam, Ali; Walling, Jeffrey S. (MDPI, 2022-05-26)
    This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for low-frequency beamforming and MIMO, as it does not require passive or LO-based phase shifters. The SCPA is ideal for use as the core element since it can perform frequency translation and data conversion, and drive an output at high power and efficiency in a compact die area. A prototype four-element beamforming TX, occupying 2mm×2.5mm, can achieve a peak output power of 24.4 dBm with a peak system efficiency (SE) of 24%, while achieving <1∘ phase resolution and <1 dB gain error. When transmitting a 15 MHz, 64-QAM long-term evolution (LTE) signal it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) of <−30 dBc and an error vector magnitude (EVM) of 3.27% RMS at 1.75 GHz. A synthesized beam pattern based on measured results from a single die achieves <0.32∘ RMS beam angle error and <0.1 dB RMS beam amplitude error.