Browsing by Author "Walling, Jeffrey Sean"

Now showing 1 - 5 of 5
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    Applying Reservoir Computing for Driver Behavior Analysis and Traffic Flow Prediction in Intelligent Transportation Systems
    Sethi, Sanchit (Virginia Tech, 2024-06-05)
    In the realm of autonomous vehicles, ensuring safety through advanced anomaly detection is crucial. This thesis integrates Reservoir Computing with temporal-aware data analysis to enhance driver behavior assessment and traffic flow prediction. Our approach combines Reservoir Computing with autoencoder-based feature extraction to analyze driving metrics from vehicle sensors, capturing complex temporal patterns efficiently. Additionally, we extend our analysis to forecast traffic flow dynamics within road networks using the same framework. We evaluate our model using the PEMS-BAY and METRA-LA datasets, encompassing diverse traffic scenarios, along with a GPS dataset of 10,000 taxis, providing real-world driving dynamics. Through a support vector machine (SVM) algorithm, we categorize drivers based on their performance, offering insights for tailored anomaly detection strategies. This research advances anomaly detection for autonomous vehicles, promoting safer driving experiences and the evolution of vehicle safety technologies. By integrating Reservoir Computing with temporal-aware data analysis, this thesis contributes to both driver behavior assessment and traffic flow prediction, addressing critical aspects of autonomous vehicle systems.
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    Design and Optimization of Temporal Encoders using Integrate-and-Fire and Leaky Integrate-and-Fire Neurons
    Anderson, Juliet Graciela (Virginia Tech, 2022-10-05)
    As Moore's law nears its limit, a new form of signal processing is needed. Neuromorphic computing has used inspiration from biology to produce a new form of signal processing by mimicking biological neural networks using electrical components. Neuromorphic computing requires less signal preprocessing than digital systems since it can encode signals directly using analog temporal encoders from Spiking Neural Networks (SNNs). These encoders receive an analog signal as an input and generate a spike or spike trains as their output. The proposed temporal encoders use latency and Inter-Spike Interval (ISI) encoding and are expected to produce a highly sensitive hardware implementation of time encoding to preprocess signals for dynamic neural processors. Two ISI and two latency encoders were designed using Integrate-and-Fire (IF) and Leaky Integrate-and-Fire (LIF) neurons and optimized to produce low area designs. The IF and LIF neurons were designed using the Global Foundries 180nm CMOS process and achieved an area of 186µm2 and 182µm2, respectively. All four encoders have a sampling frequency of 50kHz. The latency encoders achieved an average energy consumption per spike of 277nJ and 316pJ for the IF-based and LIF-based latency encoders, respectively. The ISI encoders achieved an average energy consumption per spike of 1.07uJ and 901nJ for the IF-based and LIF-based ISI encoders, respectively. Power consumption is proportional to the number of neurons employed in the encoder and the potential to reduce power consumption through layout-level simulations is presented. The LIF neuron is able to use a smaller membrane capacitance to achieve similar operability as the IF neuron and consumes less area despite having more components. This demonstrates that capacitor sizes are the main limitations of a small size in spiking neurons for SNNs. An overview of the design and layout process of the two presented neurons is discussed with tips for overcoming problems encountered. The proposed designs can result in a fast neuromorphic process by employing a frequency higher than 10kHz and by providing a hardware implementation that is efficient in multiple sectors like machine learning, medical implementations, or security systems since hardware is safer from hacks.
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    Low-Power and High Precision Sensing Circuit for a Three-Channel Electrochemical Sensor
    Longest, Dylan Henry (Virginia Tech, 2024-05-31)
    A discrete, compact, low-power sensor readout circuit that can simultaneously handle two current measurements, and one voltage measurement. This work provides a compact, low-power sensor architecture, with the intent for the serial readout to be replaced with a low-power radio frequency transmitter for continuous monitoring. The proposed circuit is highly precise with an average current draw of 21 micro amps for a sampling frequency of once per minute. The target application is livestock health monitoring, which would be done by placing the sensor and circuit inside of a cow's rumen to monitor changes in pH, lactate, and VFA levels to catch metabolic disease early.
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    A mm-Wave Switched-Capacitor RFDAC
    Hieu Minh Nguyen; Walling, Jeffrey Sean; Zhu, Anding; Staszewski, Robert Bogdan (IEEE, 2022-04)
    This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) operation. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge-combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3x frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves ${ {{P_{ out}}}>21}$ dBm, drain efficiency >36%, and system efficiency >22% while operating in the Ka-band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).
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    Optimizing Reservoir Computing Architecture for Dynamic Spectrum Sensing Applications
    Sharma, Gauri (Virginia Tech, 2024-04-25)
    Spectrum sensing in wireless communications serves as a crucial binary classification tool in cognitive radios, facilitating the detection of available radio spectrums for secondary users, especially in scenarios with high Signal-to-Noise Ratio (SNR). Leveraging Liquid State Machines (LSMs), which emulate spiking neural networks like the ones in the human brain, prove to be highly effective for real-time data monitoring for such temporal tasks. The inherent advantages of LSM-based recurrent neural networks, such as low complexity, high power efficiency, and accuracy, surpass those of traditional deep learning and conventional spectrum sensing methods. The architecture of the liquid state machine processor and its training methods are crucial for the performance of an LSM accelerator. This thesis presents one such LSM-based accelerator that explores novel architectural improvements for LSM hardware. Through the adoption of triplet-based Spike-Timing-Dependent Plasticity (STDP) and various spike encoding schemes on the spectrum dataset within the LSM, we investigate the advantages offered by these proposed techniques compared to traditional LSM models on the FPGA. FPGA boards, known for their power efficiency and low latency, are well-suited for time-critical machine learning applications. The thesis explores these novel onboard learning methods, shares the results of the suggested architectural changes, explains the trade-offs involved, and explores how the improved LSM model's accuracy can benefit different classification tasks. Additionally, we outline the future research directions aimed at further enhancing the accuracy of these models.