Browsing by Author "Xu, Peng"

Now showing 1 - 4 of 4
  • Thumbnail Image
    Building A Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage
    Xu, Peng; Zhao, Nannan; Wan, Jiguang; Liu, Wei; Chen, Shuning; Zhou, Yuanhui; Albahar, Hadeel; Liu, Hanyang; Tang, Liu; Tan, Zhihu (ACM, 2022-05-25)
    The explosive growth of modern web-scale applications has made cost-effectiveness a primary design goal for their underlying databases. As a backbone of modern databases, LSM-tree based key-value stores (LSM store) face limited storage options. They are either designed for local storage that is relatively small, expensive, and fast or for cloud storage that offers larger capacities at reduced costs but slower. Designing an LSM store by integrating local storage with cloud storage services is a promising way to balance the cost and performance. However, such design faces challenges such as data reorganization, metadata overhead, and reliability issues. In this paper, we propose RocksMash, a fast and efficient LSM store that uses local storage to store frequently accessed data and metadata while using cloud to hold the rest of the data to achieve cost-effectiveness. To improve metadata space-efficiency and read performance, RocksMash uses an LSM-aware persistent cache that stores metadata in a space-efficient way and stores popular data blocks by using compaction-aware layouts. Moreover, RocksMash uses an extended write-ahead log for fast parallel data recovery. We implemented RocksMash by embedding these designs into RocksDB. The evaluation results show that RocksMash improves the performance by up to 1.7x compared to the state-of-the-art schemes and delivers high reliability, cost-effectiveness, and fast recovery.
  • Thumbnail Image
    Design of Joint Verification-Correction Strategies  for Engineered Systems
    Xu, Peng (Virginia Tech, 2022-06-28)
    System verification is a critical process in the development of engineered systems. Engineers gain confidence in the correct functionality of the system by executing system verification. Traditionally, system verification is implemented by conducting a verification strategy (VS) consisting of verification activities (VA). A VS can be generated using industry standards, expert experience, or quantitative-based methods. However, two limitations exist in these previous studies. First, as an essential part of system verification, correction activities (CA) are used to correct system errors or defects identified by VAs. However, CAs are usually simplified and treated as a component associated with VAs instead of independent decisions. Even though this simplification may accelerate the VS design, it results in inferior VSs because the optimization of correction decisions is ignored. Second, current methods have not handled the issue of complex engineered systems. As the number of activities increases, the magnitude of the possible VSs becomes so large that finding the optimal VS is impossible or impractical. Therefore, these limitations leave room for improving the VS design, especially for complex engineered systems. This dissertation presents a joint verification-correction model (JVCM) to address these gaps. The basic idea of this model is to provide an engineering paradigm for complex engineered systems that simultaneously consider decisions about VAs and CAs. The accompanying research problem is to develop a modeling and analysis framework to solve for joint verification-correction strategies (JVCS). This dissertation aims to address them in three steps. First, verification processes (VP) are modeled mathematically to capture the impacts of VAs and CAs. Second, a JVCM with small strategy spaces is established with all conditions of a VP. A modified backward induction method is proposed to solve for an optimal JVCS in small strategy spaces. Third, a UCB-based tree search approach is designed to find near-optimal JVCSs in large strategy spaces. A case study is conducted and analyzed in each step to show the feasibility of the proposed models and methods.
  • Thumbnail Image
    Multiphase clamp coupled-buck converter and magnetic integration
    (United States Patent and Trademark Office, 2004-08-31)
    Voltage regulation, transient response and efficiency of a voltage regulator module (VRM) is improved where short duty cycles are necessitated by large differentials of input and output voltage by including at least one clamping of a tap of an inductance in series with an output of each of a plurality of parallel branches or phases which are switched in a complementary fashion or providing coupling between inductors of respective phases. Such coupling between inductors is achieved in a small module with an integrated magnetic structure. Reduced component counts are achieved while deriving built-in input and output filters. Principals of the invention can be extended to isolation applications and push-pull forward converts, in particular. A lossless clamping circuit is also provided allowing spike currents to be suppressed while returning power to the output of the VRM.
  • Thumbnail Image
    Multiphase Voltage Regulator Modules with Magnetic Integration to Power Microprocessors
    Xu, Peng (Virginia Tech, 2002-01-15)
    Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed. Today's multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter. By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure. Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice.