Journal Articles, Hindawi Press

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https://hdl.handle.net/10919/78797

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Applications of Different Weighting Schemes to Improve Pathway-Based Analysis
Ha, Sook S.; Kim, Inyoung; Wang, Yue; Xuan, Jianhua (Hindawi, 2011-05-22)
Conventionally, pathway-based analysis assumes that genes in a pathway equally contribute to a biological function, thus assigning uniform weight to genes. However, this assumption has been proved incorrect, and applying uniform weight in the pathway analysis may not be an appropriate approach for the tasks like molecular classification of diseases, as genes in a functional group may have different predicting power. Hence, we propose to use different weights to genes in pathway-based analysis and devise four weighting schemes. We applied them in two existing pathway analysis methods using both real and simulated gene expression data for pathways. Among all schemes, random weighting scheme, which generates random weights and selects optimal weights minimizing an objective function, performs best in terms of 𝑷 value or error rate reduction. Weighting changes pathway scoring and brings up some new significant pathways, leading to the detection of disease-related genes that are missed under uniform weight.
Block-Level Logic Extraction from CMOS VLSILayouts
Bhasin, Inderpreet; Tront, Joseph G. (Hindawi, 1994-01-01)
This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level descriptionof a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to thatof a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be usedto identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to thecircuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logicblocks composed of these gates are then identified. More complex blocks which contain blocks already identifiedare recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It canprovide a connectivity check for a circuit.
BSML: A Binding Schema Markup Language for Data Interchange in Problem Solving Environments
Verstak, Alex; Ramakrishnan, Naren; Watson, Layne T.; He, Jian; Shaffer, Clifford A.; Bae, Kyung Kyoon; Jiang, Jing; Tranter, William H.; Rappaport, Theodore S. (Hindawi, 2003-01-01)
We describe a binding schema markup language (BSML) for describing data interchange between scientific codes. Such a facility is an important constituent of scientific problem solving environments (PSEs). BSML is designed to integrate with a PSE or application composition system that views model specification and execution as a problem of managing semistructured data. The data interchange problem is addressed by three techniques for processing semistructured data: validation, binding, and conversion. We present BSML and describe its application to a PSE for wireless communications system design.
Control of Rotary Cranes Using Fuzzy Logic
Al-mousa, Amjed A.; Nayfeh, Ali H.; Kachroo, Pushkin (Hindawi, 2003-01-01)
Rotary cranes (tower cranes) are common industrial structures that are used in building construction, factories, and harbors. These cranes are usually operated manually. With the size of these cranes becoming larger and the motion expected to be faster, the process of controlling them has become difficult without using automatic control methods. In general, the movement of cranes has no prescribed path. Cranes have to be run under different operating conditions, which makes closed-loop control attractive.In this work a fuzzy logic controller is introduced with the idea of “split-horizon”; that is, fuzzy inference engines (FIE) are used for tracking the position and others are used for damping the load oscillations. The controller consists of two independent sub-controllers: radial and rotational. Each of these controllers has two fuzzy inference engines (FIE). Computer simulations are used to verify the performance of the controller. Three simulation cases are presented. In the first case, the crane is operated in the gantry (radial) mode in which the trolley moves along the jib while the jib is fixed. In the second case (rotary mode), the trolley moves along the jib and the jib rotates. In the third case, the trolley and jib are fixed while the load is given an initial disturbance. The results from the simulations show that the fuzzy controller is capable of keeping the load-oscillation angles small throughout the maneuvers while completing the maneuvers in relatively reasonable times.
Design and Implementation of a DSP-Based MIMO System Prototype for Real-Time Demonstration and Indoor Channel Measurements
Mostafa, Raqibul; Gozali, Ran; Palat, Ramesh Chembil; Robert, Max; Newhall, William G.; Woerner, Brian D.; Reed, Jeffrey H. (2005-09-21)
The design and implementation of the Virginia Tech Space-Time Advanced Radio (VT-STAR), a multiple antenna element space-time (ST) processing prototype testbed, is presented. The testbed is a research tool for comparing practical and theoretical performance metrics (e.g., throughput, link reliability) in different wireless channel conditions. The prototype builds around software-defined radio (SDR) concepts on a DSP platform and provides the flexibility to implement various forms of ST techniques. Different components of the system are described in detail, including the software implementation, I/O schemes with custom hardware, and data transfer mechanisms between the DSP and the host PC. Two different example realizations are presented, a real-time demonstration and an offline measurement tool. Finally, some representative measurement results obtained in indoor environments are presented. These results show VT-STAR to be a promising tool for performing MIMO experiments and generating channel measurements that can complement simulation studies in this area.
Dynamic Hardware Development
Craven, Stephen; Athanas, Peter M. (Hindawi, 2008-10-15)
Applications that leverage the dynamic partial reconfigurability of modern FPGAs arefew, owing in large part to the lack of suitable tools and techniques to create them. Whilethe trend in digital design is towards higher levels of design abstractions, forgoing hardwaredescription languages in some cases for high-level languages, the development of a reconfigurabledesign requires developers to work at a low level and contend with many poorlydocumented architecture-specific aspects. This paper discusses the creation of a high-leveldevelopment environment for reconfigurable designs that leverage an existing high-level synthesistool to enable the design, simulation, and implementation of dynamically reconfigurablehardware solely from a specification written in C. Unlike previous attempts, this approachencompasses the entirety of design and implementation, enables self-re-configurationthrough an embedded controller, and inherently handles partial reconfiguration. Benchmarkingnumbers are provided, which validate the productivity enhancements this approachprovides.
An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits
Lee, Hyung K.; Ha, Dong S. (Hindawi, 1994-01-01)
In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, calledSOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into anequivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives testpatterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set sizeare introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANOachieves high SOP fault coverage and short processing time.
Efficient Design of Flexible and Low Cost Paper-Based Inkjet-Printed Antenna
Mansour, A. M.; Shehata, Nader; Hamza, B. M.; Rizk, M. R. M. (Hindawi, 2015-09-29)
A new, efficient, flexible, and cheap antenna designed at 1.57 GHz microstrip patch antenna based on simple inkjet printer with improved performance using silver nanoparticles ink is developed. The antenna is printed on a kind of flexible substrate “glossy paper,” to offer the advantage of light and flexibility for different applications. The performance of silver nanoparticles ink has been studied through inkjet printing versus postsynthesis annealing and multilayer printing. The conductivity has been improved to have promising values up to 2 Ω/cm at temperatures up to 180°C. The surface morphology of the circuits has been analyzed using SEM with mean diameter of the nanoparticles around 100 nm, uniform surface distribution, and mean thickness of the printed layer around 230 microns. Also, a simple design of a coplanar waveguide (CPW) monopole Z-shaped antenna has been considered as an application of fabricated printed antenna using the studied silver nanoparticles ink through a cheap printer.
Encryption of 3D Point Cloud Object with Deformed Fringe
Yang, Xin; Zhang, Hongbo (Hindawi, 2016-02-15)
A 3D point cloud object encryption method was proposed with this study. With the method, a mapping relationship between 3D coordinates was formulated and coordinate was transformed to deformed fringe by a phase coding method. The deformed fringe and gray image were used for encryption and decryption with simulated off-axis digital Fresnel hologram. Results indicated that the proposed method is able to accurately decrypt the coordinates and gray image of the 3D object. The method is also robust against occlusion attacks.
Exploiting Process Locality of Reference in RTL Simulation Acceleration
Patterson, Cameron D.; Blumer, Aric David (2007-12-11)
With the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subset of the simulation processes is executing at any given time, a quality called executive locality of reference. The efficiency of acceleration hardware can be improved when it is used as a process cache. Run-time adaptations are made to ensure that acceleration resources are not wasted on idle processes, and these adaptations may be affected through process migration between software and hardware. An implementation of an embedded, FPGA-based migration system is described, and empirical data are obtained for use in mathematical and algorithmic modeling of more complex acceleration systems.
FPGA Dynamic Power Minimization through Placement and Routing Constraints
Wang, Li; French, Matthew; Davoodi, Azadeh; Agarwal, Deepak (2006-08-29)
Field-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.
Genetic spot optimization for peak power estimation in large VLSI circuits
Hsiao, Michael S. (Hindawi, 2001-07-10)
Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication
Judge, Lyndon; Mane, Suvarna; Schaumont, Patrick R. (Hindawi, 2012-09-01)
Elliptic curve cryptography (ECC) has become a popular public key cryptography standard. The security of ECC is due to the difficulty of solving the elliptic curve discrete logarithm problem (ECDLP). In this paper, we demonstrate a successful attack on ECC over prime field using the Pollard rho algorithm implemented on a hardware-software cointegrated platform. We propose a high-performance architecture for multiplication over prime field using specialized DSP blocks in the FPGA. We characterize this architecture by exploring the design space to determine the optimal integer basis for polynomial representation and we demonstrate an efficient mapping of this design to multiple standard prime field elliptic curves. We use the resulting modular multiplier to demonstrate low-latency multiplications for curves secp112r1 and P-192. We apply our modular multiplier to implement a complete attack on secp112r1 using a Nallatech FSB-Compute platform with Virtex-5 FPGA. The measured performance of the resulting design is 114 cycles per Pollard rho step at 100 MHz, which gives 878 K iterations per second per ECC core. We extend this design to a multicore ECDLP implementation that achieves 14.05 M iterations per second with 16 parallel point addition cores.
Hybrid Experiential-Heuristic Cognitive Radio Engine Architecture and Implementation
Amanna, Ashwin E.; Ali, Daniel; Fitch, David Gonzalez; Reed, Jeffrey H. (Hindawi, 2012-05-16)
The concept of cognitive radio (CR) focuses on devices that can sense their environment, adapt configuration parameters, and learn from past behaviors. Architectures tend towards simplified decision-making algorithms inspired by human cognition. Initial works defined cognitive engines (CEs) founded on heuristics, such as genetic algorithms (GAs), and case-based reasoning (CBR) experiential learning algorithms. This hybrid architecture enables both long-term learning, faster decisions based on past experience, and capability to still adapt to new environments. This paper details an autonomous implementation of a hybrid CBR-GA CE architecture on a universal serial radio peripheral (USRP) software-defined radio focused on link adaptation. Details include overall process flow, case base structure/retrieval method, estimation approach within the GA, and hardware-software lessons learned. Unique solutions to realizing the concept include mechanisms for combining vector distance and past fitness into an aggregate quantification of similarity. Over-the-air performance under several interference conditions is measured using signal-to-noise ratio, packet error rate, spectral efficiency, and throughput as observable metrics. Results indicate that the CE is successfully able to autonomously change transmit power, modulation/coding, and packet size to maintain the link while a non-cognitive approach loses connectivity. Solutions to existing shortcomings are proposed for improving case-base searching and performance estimation methods.
Improved Diagnostics Using Polarization Imaging and Artificial Neural Networks
Xuan, Jianhua; Klimach, Uwe; Zhao, Hongzhi; Chen, Qiushui; Zou, Yingyin; Wang, Yue (Hindawi, 2007-11-06)
In recent years, there has been an increasing interest in studying the propagation of polarized light in biological cells and tissues. This paper presents a novel approach to cell or tissue imaging using a full Stokes imaging system with advanced polarization image analysis algorithms for improved diagnostics. The key component of the Stokes imaging system is the electrically tunable retarder, enabling high-speed operation of the system to acquire four intensity images sequentially. From the acquired intensity images, four Stokes vector images can be computed to obtain complete polarization information. Polarization image analysis algorithms are then developed to analyze Stokes polarization images for cell or tissue classification. Specifically, wavelet transforms are first applied to the Stokes components for initial feature analysis and extraction. Artificial neural networks (ANNs) are then used to extract diagnostic features for improved classification and prediction. In this study, phantom experiments have been conducted using a prototyped Stokes polarization imaging device. In particular, several types of phantoms, consisting of polystyrene latex spheres in various diameters, were prepared to simulate different conditions of epidermal layer of skin. The experimental results from phantom studies and a plant cell study show that the classification performance using Stokes images is significantly improved over that using the intensity image only.
Modeling and Reconstruction of Mixed Functional and Molecular Patterns
Wang, Yue; Xuan, Jianhua; Srikanchana, Rujirutana; Choyke, Peter L. (Hindawi, 2006-01-17)
Functional medical imaging promises powerful tools for thevisualization and elucidation of important disease-causingbiological processes in living tissue. Recent research aims todissect the distribution or expression of multiple biomarkersassociated with disease progression or response, where the signalsoften represent a composite of more than one distinct sourceindependent of spatial resolution. Formulating the task as a blindsource separation or composite signal factorization problem, wereport here a statistically principled method for modeling andreconstruction of mixed functional or molecular patterns. Thecomputational algorithm is based on a latent variable model whoseparameters are estimated using clustered component analysis. Wedemonstrate the principle and performance of the approaches on thebreast cancer data sets acquired by dynamic contrast-enhancedmagnetic resonance imaging.
Multisensor Processing for Signal Extraction and Applications
Chi, Chong-Yung; Lee, Ta-Sung; Luo, Zhi-Quan; Wang, Yue; Yao, Kung (2006-11-01)
A new characterization method for delay and power dissipation of standard library cells
Sulistyo, Jos B.; Ha, Dong S. (Hindawi, 2002-11-01)
A simplified method for characterization of standard library cells based on the linear delay model is presented in this paper. The linear model is chosen as it allows rapid characterization with a modest number of simulations, while achieving acceptable accuracy. All the parameters of cell delays are defined as 50%-to-50% delays, as distinguished from 50%-to-threshold or threshold-to-50% often used in commercial tools. We found that the 50%-to-50% definition of delays is more consistent and leads to closed-form formula. A subset of library cells in a 0.25 mum technology was characterized using the proposed technique. A test circuit was subsequently generated and simulated to determine the accuracy of the proposed characterization method. SPICE simulations on the test circuit show that the timing estimations obtained through the proposed method is accurate to within 5.6%, and the power estimation was accurate to 4.2%, ignoring parasitics on interconnections.
Nonlinear Speed Control of Switched Reluctance Motor Drives Taking into Account Mutual Inductance
Alrifai, M.; Zribi, M.; Krishnan, R.; Rayan, M. (Hindawi, 2008-03-25)
A speed control algorithm is proposed for variable speed switched reluctance motor (SRM) drives taking into account the effects of mutual inductances. The control scheme adopts two-phase excitation; exciting two adjacent phases can overcome the problems associated with single-phase excitation such as large torque ripple, increased acoustic noise, and rotor shaft fatigues. The effects of mutual coupling between two adjacent phases and their contribution to the generated electromagnetic torque are considered in the design of the proposed control scheme for the motor. The proposed controller guarantees the convergence of the currents and the rotor speed of the motor to their desired values. Simulation results are given to illustrate the developed theory; the simulation studies show that the proposed controller works well. Moreover, the simulation results indicate that the proposed controller is robust to changes in the parameters of the motor and to changes in the load torque.
Nonrigid Medical Image Registration by Finite-Element Deformable Sheet-Curve Models
Xuan, Jianhua; Wang, Yue; Freedman, Matthew T.; Adali, Tulay; Shields, Peter (Hindawi, 2006-08-13)
Image-based change quantitation has been recognized as a promisingtool for accurate assessment of tumor's early response tochemoprevention in cancer research. For example, various changeson breast density and vascularity in glandular tissue are theindicators of early response to treatment. Accurate extraction ofglandular tissue from pre- and postcontrast magnetic resonance(MR) images requires a nonrigid registration of sequential MRimages embedded with local deformations. This paper reports anewly developed registration method that aligns MR breast imagesusing finite-element deformable sheet-curve models. Specifically,deformable curves are constructed to match the boundariesdynamically, while a deformable sheet of thin-plate splines isdesigned to model complex local deformations. The experimentalresults on both digital phantoms and real MR breast images usingthe new method have been compared to point-based thin-plate-spline(TPS) approach, and have demonstrated a significant and robustimprovement in both boundary alignment and local deformationrecovery.

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