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dc.contributor.authorChaubal, Aditya Prakashen_US
dc.date.accessioned2011-08-06T16:06:17Z
dc.date.available2011-08-06T16:06:17Z
dc.date.issued2004-08-23en_US
dc.identifier.otheretd-07262004-170319en_US
dc.identifier.urihttp://hdl.handle.net/10919/10098
dc.description.abstractThere is currently a strong trend towards embedding Internet capabilities into electronics and everyday appliances. Most network controllers used in small appliances or for specialized purposes are built using micro controllers. However there are many applications where a hardware-oriented approach using Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) is more suitable. One of the features of FPGAs that cannot be integrated into ASICs is runtime reconfiguration in which, certain portions of the chip are reconfigured at runtime while the other parts continue to operate normally. This feature is required for network controllers with multiple data transfer channels that need to preserve the state of the static channels while reconfiguration is taking place. It is also required for controllers with space constraints in terms of FPGA resources or time constraints in terms of reconfiguration times. This thesis explores the impact of partial reconfiguration on the performance of a network controller. An FPGA-based network controller that supports partial reconfiguration has been designed and constructed. Partial bitstreams that can configure certain channels of the network controller without a ecting the functioning of others have been created. Experiments have been performed that quantify the manner in which, the performance of the controller can be changed by loading these partial bitstreams onto the FPGA. These experiments demonstrated the advantages of using partial reconfiguration to change network-related parameters at runtime to optimize performance of the network controller.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartachaubal_thesis_etd.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectFPGAen_US
dc.subjectPartial reconfigurationen_US
dc.subjectNetworken_US
dc.subjectVirtexen_US
dc.subjectXilinxen_US
dc.subjectIIM7010en_US
dc.titleDesign and Implementation of an FPGA-based Partially Reconfigurable Network Controlleren_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberJones, Mark T.en_US
dc.contributor.committeememberPatterson, Cameron D.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07262004-170319en_US
dc.date.sdate2004-07-26en_US
dc.date.rdate2004-09-03
dc.date.adate2004-09-03en_US


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