Show simple item record

dc.contributor.authorKathuria, Tarunen
dc.date.accessioned2021-01-13T07:00:18Zen
dc.date.available2021-01-13T07:00:18Zen
dc.date.issued2019-07-22en
dc.identifier.othervt_gsexam:21837en
dc.identifier.urihttp://hdl.handle.net/10919/101862en
dc.description.abstractSide-channel leakage, caused by imperfect implementation of cryptographic algorithms in hardware, has become a serious security threat for connected devices that generate and process sensitive data. This side-channel leakage can divulge secret information in the form of power consumption or electromagnetic emissions. The side-channel leakage of a crytographic device is commonly assessed after tape-out on a physical prototype. This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which evaluates the power-based side-channel leakage of an integrated circuit at design time. By combining side-channel leakage assessment with power simulations on the gate-level netlist, GLA is able to pinpoint the leakiest cells in the netlist in addition to assessing the overall side-channel vulnerability to side-channel leakage. As the power traces obtained from power simulations are noiseless, GLA is able to precisely locate the sources of side-channel leakage with fewer measurements than on a physical prototype. The thesis applies the methodology on the design of a encryption co-processor to analyze sources of side-channel leakage. Once the gate-level leakage sources are identified, this thesis presents a logic level replacement strategy for the leakage sources that can thwart side-channel leakage. The countermeasures presented selectively replaces gate-level cells with a secure logic style effectively removing the side-channel leakage with minimal impact in area. The assessment methodology along with the countermeasures demonstrated is a turnkey solution for IP module designers and is also applicable to larger system level designs.en
dc.format.mediumETDen
dc.publisherVirginia Techen
dc.rightsThis item is protected by copyright and/or related rights. Some uses of this item may be deemed fair and permitted by law even without permission from the rights holder(s), or the rights holder(s) may have licensed the work for use under certain conditions. For other uses you need to obtain permission from the rights holder(s).en
dc.subjectSide-channel leakageen
dc.subjectCountermeasuresen
dc.subjectPower analysis attacksen
dc.titleGate-level Leakage Assessment and Mitigationen
dc.typeThesisen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineComputer Engineeringen
dc.contributor.committeechairSchaumont, Patrick Roberten
dc.contributor.committeememberPatterson, Cameron D.en
dc.contributor.committeememberJian, Xunen


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record