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dc.contributor.authorLiu, Xiaoen_US
dc.date.accessioned2011-08-22T19:02:33Z
dc.date.available2011-08-22T19:02:33Z
dc.date.issued2004-06-10en_US
dc.identifier.otheretd-07302004-093710en_US
dc.identifier.urihttp://hdl.handle.net/10919/11213
dc.description.abstractWith ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of functional test patterns and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based delay testing and develops efficient Automatic Test Pattern Generation (ATPG) and Design-for-testability (DFT) algorithms for delay testing. In the dissertation, two algorithms are first proposed for computing and applying transition test patterns using stuck-at test vectors, thus avoiding the need for a transition fault test generator. The experimental results show that we can improve both test data volume and test application time by 46.5% over a commercial transition ATPG tool. Secondly, we propose a hybrid scan-based delay testing technique for compact and high fault coverage test set, which combines the advantages of both the skewed-load and broadside test application methods. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach, with very little hardware overhead. Thirdly, we propose and develop a constrained ATPG algorithm for scan-based delay testing, which addresses the overtesting problem due to the possible detection of functionally untestable faults in scan-based testing. The experimental results show that our method efficiently generates a test set for functionally testable transition faults and reduces the yield loss due to overtesting of functionally untestable transition faults. Finally, a new approach on identifying functionally untestable transition faults in non-scan sequential circuits is presented. We formulate a new dominance relationship for transition faults and use it to help identify more untestable transition faults on top of a fault-independent method based on static implications. The experimental results for ISCAS89 sequential benchmark circuits show that our approach can identify many more functionally untestable transition faults than previously reported.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartxiaoliu_dissertation.pdfen_US
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectDFTen_US
dc.subjectATPGen_US
dc.subjecttransition faulten_US
dc.subjecttestingen_US
dc.subjectdelay testingen_US
dc.titleATPG and DFT Algorithms for Delay Fault Testingen_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairHsiao, Michael S.en_US
dc.contributor.committeememberShimozono, Mark M.en_US
dc.contributor.committeememberMartin, Thomas L.en_US
dc.contributor.committeememberHa, Dong Samen_US
dc.contributor.committeememberBuehrer, R. Michaelen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07302004-093710en_US
dc.date.sdate2004-07-30en_US
dc.date.rdate2004-08-03
dc.date.adate2004-08-03en_US


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