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dc.contributor.authorPatterson, Cameron D.en_US
dc.contributor.authorBlumer, Aric Daviden_US
dc.date.accessioned2012-08-24T12:07:50Z
dc.date.available2012-08-24T12:07:50Z
dc.date.issued2007-12-11
dc.identifier.citationEURASIP Journal on Embedded Systems. 2007 Dec 11;2008(1):369040en_US
dc.identifier.urihttp://hdl.handle.net/10919/18911
dc.description.abstractWith the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subset of the simulation processes is executing at any given time, a quality called executive locality of reference. The efficiency of acceleration hardware can be improved when it is used as a process cache. Run-time adaptations are made to ensure that acceleration resources are not wasted on idle processes, and these adaptations may be affected through process migration between software and hardware. An implementation of an embedded, FPGA-based migration system is described, and empirical data are obtained for use in mathematical and algorithmic modeling of more complex acceleration systems.en_US
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.rightsCreative Commons Attribution 4.0 International*
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/*
dc.titleExploiting Process Locality of Reference in RTL Simulation Accelerationen_US
dc.typeArticle - Refereed
dc.date.updated2012-08-24T12:07:50Z
dc.description.versionPeer Reviewed
dc.rights.holderAricD Blumer et al.; licensee BioMed Central Ltd.en_US
dc.title.serialEURASIP Journal on Embedded Systems
dc.identifier.doihttps://doi.org/10.1155/2008/369040
dc.type.dcmitypeText


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Creative Commons Attribution 4.0 International
License: Creative Commons Attribution 4.0 International