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dc.contributor.authorMacias, Nicholas Jen_US
dc.date.accessioned2014-03-14T20:11:54Z
dc.date.available2014-03-14T20:11:54Z
dc.date.issued2011-04-29en_US
dc.identifier.otheretd-05112011-173844en_US
dc.identifier.urihttp://hdl.handle.net/10919/27665
dc.description.abstractAs VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. An architecture is presented that satisfies these hypothesis, and the motivation behind the hypothesis is further explained. The use of this architectureâ s unique features to implement an efficient, defect-tolerant parallel bootstrap system is discussed. A detailed methodology for implementing this system in vivo is described. A sample problem â simulation of heat flow â is presented, and its solution using the proposed architecture is described in detail. A comparison is made between the proposed architecture and a set of contemporary architectures, and the former is shown to have desirable performance in a number of areas. Conclusion are given, and plans for future work are presented.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartMacias_NJ_D_2011.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectnon-dualismen_US
dc.subjectfault handlingen_US
dc.subjectparallelismen_US
dc.subjectFPGAen_US
dc.subjectself-modifyingen_US
dc.subjectself-configurableen_US
dc.subjectreconfigurableen_US
dc.subjectAvogadro machineen_US
dc.titleSelf-Modifying Circuitry for Efficient, Defect-Tolerant Handling of Trillion-element Reconfigurable Devicesen_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
thesis.degree.namePhDen_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberAbbott, A. Lynnen_US
dc.contributor.committeememberJones, Alexen_US
dc.contributor.committeememberMartin, Thomas L.en_US
dc.contributor.committeememberPatterson, Cameron D.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-05112011-173844/en_US
dc.date.sdate2011-05-11en_US
dc.date.rdate2011-05-31
dc.date.adate2011-05-31en_US


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