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dc.contributor.authorBlagojevic, Filipen_US
dc.date.accessioned2014-03-14T20:12:44Z
dc.date.available2014-03-14T20:12:44Z
dc.date.issued2008-05-30en_US
dc.identifier.otheretd-06052008-012156en_US
dc.identifier.urihttp://hdl.handle.net/10919/27952
dc.description.abstractWe explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate conventional cores that run legacy codes with specialized cores that serve as computational accelerators. The term multi-grain parallelism refers to the exposure of multiple dimensions of parallelism from within the runtime system, so as to best exploit a parallel architecture with heterogeneous computational capabilities between its cores and execution units. To maximize performance on heterogeneous multi-core processors, programs need to expose multiple dimensions of parallelism simultaneously. Unfortunately, programming with multiple dimensions of parallelism is to date an ad hoc process, relying heavily on the intuition and skill of programmers. Formal techniques are needed to optimize multi-dimensional parallel program designs. We investigate user- and kernel-level schedulers that dynamically "rightsize" the dimensions and degrees of parallelism on the asymmetric parallel platforms. The schedulers address the problem of mapping application-specific concurrency to an architecture with multiple hardware layers of parallelism, without requiring programmer intervention or sophisticated compiler support. Our runtime environment outperforms the native Linux and MPI scheduling environment by up to a factor of 2.7. We also present a model of multi-dimensional parallel computation for steering the parallelization process on heterogeneous multi-core processors. The model predicts with high accuracy the execution time and scalability of a program using conventional processors and accelerators simultaneously. More specifically, the model reveals optimal degrees of multi-dimensional, task-level and data-level concurrency, to maximize performance across cores. We evaluate our runtime policies as well as the performance model we developed, on an IBM Cell BladeCenter, as well as on a cluster composed of Playstation3 nodes, using two realistic bioinformatics applications.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartdissertation.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectprocess schedulingen_US
dc.subjectperformance predictionen_US
dc.subjecthigh-performance computingen_US
dc.subjectruntime adaptationen_US
dc.subjectMulticore processorsen_US
dc.subjectCell BEen_US
dc.titleScheduling on Asymmetric Architecturesen_US
dc.typeDissertationen_US
dc.contributor.departmentComputer Scienceen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineComputer Scienceen_US
dc.contributor.committeechairNikolopoulos, Dimitrios S.en_US
dc.contributor.committeememberRibbens, Calvin J.en_US
dc.contributor.committeememberLowenthal, David K.en_US
dc.contributor.committeememberFeng, Wu-Chunen_US
dc.contributor.committeememberCameron, Kirk W.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06052008-012156/en_US
dc.date.sdate2008-06-05en_US
dc.date.rdate2009-07-22
dc.date.adate2008-07-22en_US


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