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dc.contributor.authorWen, Sihuaen_US
dc.date.accessioned2014-03-14T20:15:18Z
dc.date.available2014-03-14T20:15:18Z
dc.date.issued2002-08-02en_US
dc.identifier.otheretd-08162002-233352en_US
dc.identifier.urihttp://hdl.handle.net/10919/28679
dc.description.abstractThis research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartChapter_2.pdfen_US
dc.relation.haspartReference.pdfen_US
dc.relation.haspartChapter_5.pdfen_US
dc.relation.haspartChapter_1.pdfen_US
dc.relation.haspartChapter_6.pdfen_US
dc.relation.haspartTitle_pages.pdfen_US
dc.relation.haspartChapter_3.pdfen_US
dc.relation.haspartVita.pdfen_US
dc.relation.haspartChapter_4.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectBGAen_US
dc.subjectconverteren_US
dc.subjectassemblyen_US
dc.subjectflexen_US
dc.subjectflexible circuiten_US
dc.titleDesign and Analyses of a Dimple Array Interconnect Technique for Power Electronics Packagingen_US
dc.typeDissertationen_US
dc.contributor.departmentCenter for Power Electronics Systemsen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineMaterials Science and Engineeringen_US
dc.contributor.committeechairLu, Guo-Quanen_US
dc.contributor.committeememberGuido, Louis J.en_US
dc.contributor.committeememberNelson, Douglas J.en_US
dc.contributor.committeememberSuchicital, Carlos T. A.en_US
dc.contributor.committeemembervan Wyk, Jacobus Danielen_US
dc.contributor.committeememberBoroyevich, Dushanen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08162002-233352/en_US
dc.date.sdate2002-08-16en_US
dc.date.rdate2003-08-27
dc.date.adate2002-08-27en_US


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