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dc.contributor.authorBai, Yumingen_US
dc.date.accessioned2014-03-14T20:16:04Z
dc.date.available2014-03-14T20:16:04Z
dc.date.issued2003-08-28en_US
dc.identifier.otheretd-09092003-235330en_US
dc.identifier.urihttp://hdl.handle.net/10919/28915
dc.description.abstractEvolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartdissertation.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectOptimizationen_US
dc.subjectBuck Converteren_US
dc.subjectTrench MOSFETen_US
dc.titleOptimization of Power MOSFET for High-Frequency Synchronous Buck Converteren_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairHuang, Alex Q.en_US
dc.contributor.committeememberBoroyevich, Dushanen_US
dc.contributor.committeememberLai, Jih-Sheng Jasonen_US
dc.contributor.committeememberLu, Guo-Quanen_US
dc.contributor.committeememberHa, Dong Samen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-09092003-235330/en_US
dc.date.sdate2003-09-09en_US
dc.date.rdate2006-09-12
dc.date.adate2003-09-12en_US


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