VTechWorks staff will be away for the Thanksgiving holiday beginning at noon on Wednesday, November 22, through Friday, November 24, and will not be replying to requests during this time. Thank you for your patience, and happy holidays!
A Design Assembly Technique for FPGA Back-End Acceleration
Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.