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dc.contributor.authorFrangieh, Tannousen
dc.date.accessioned2014-03-14T20:17:11Zen
dc.date.available2014-03-14T20:17:11Zen
dc.date.issued2012-09-28en
dc.identifier.otheretd-10082012-021855en
dc.identifier.urihttp://hdl.handle.net/10919/29225en
dc.description.abstractLong wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.en
dc.publisherVirginia Techen
dc.relation.haspartFrangieh_T_D_2012.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectConfigurable Computingen
dc.subjectFPGA Productivityen
dc.subjectDesign Assembly Flowen
dc.subjectElectronic Design Automationen
dc.subjectDesign Reuseen
dc.titleA Design Assembly Technique for FPGA Back-End Accelerationen
dc.typeDissertationen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreePh. D.en
thesis.degree.namePh. D.en
thesis.degree.leveldoctoralen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical and Computer Engineeringen
dc.contributor.committeechairAthanas, Peter M.en
dc.contributor.committeememberSchaumont, Patrick Roberten
dc.contributor.committeememberNelson, Brent E.en
dc.contributor.committeememberDietrich, Carl B.en
dc.contributor.committeememberFeng, Wu-Chunen
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-10082012-021855/en
dc.date.sdate2012-10-08en
dc.date.rdate2012-10-19en
dc.date.adate2012-10-19en


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