This dissertation provides a study of synchronization and quantization issues in implementing a multistage receiver in fixed-point Digital Signal Processing (DSP) hardware. Current multistage receiver analysis has neglected the effects of synchronization and quantization; however, these effects can degrade system performance and therefore decrease overall system capacity. The first objective is to analyze and simulate various effects of synchronization in a multistage system. These effects include the effect of unsynchronized users on the bit error rate (BER) of synchronized users, and determining whether interference cancellation can be used to improve the synchronization time. This information is used to determine whether synchronization will limit overall system capacity. Both analytical and simulation techniques are presented. The second objective is to study the effects of quantization on the performance of the multistage receiver. A DSP implementation of a practical receiver will require a DSP chip with a fewer number of bits than the computer chips typically used in simulation of receiver performance. Therefore, the DSP implementation performs poorer than the simulation results predict. In addition, a fixed-point implementation is often favored over a floating-point implementation, due to the high processing requirements necessitated by the high chip rate. This further degrades performance because of the limited dynamic range available with fixed-point arithmetic. The performance of the receiver using a fixed-point implementation is analyzed and simulated.

We also relate these topics to other important issues in the hardware implementation of multistage receivers, including the effects of frequency offsets at the receiver and developing a multiuser air protocol interface (API). This dissertation represents a contribution to the ongoing hardware development effort in multistage receivers at Virginia Tech.