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dc.contributor.authorBittner, Ray Albert Jr.en_US
dc.date.accessioned2014-03-14T20:21:53Z
dc.date.available2014-03-14T20:21:53Z
dc.date.issued1997-01-23en_US
dc.identifier.otheretd-38419290973280en_US
dc.identifier.urihttp://hdl.handle.net/10919/30499
dc.description.abstractIn the past, various approaches to the high performance numerical computing problem have been explored. Recently, researchers have begun to explore the possibilities of using Field Programmable Gate Arrays (FPGAs) to solve numerically intensive problems. FPGAs offer the possibility of customization to any given application, while not sacrificing applicability to a wide problem domain. Further, the implementation of data flow graphs directly in silicon makes FPGAs very attractive for these types of problems. Unfortunately, current FPGAs suffer from a number of inadequacies with respect to the task. They have lower transistor densities than ASIC solutions, and hence less potential computational power per unit area. Routing overhead generally makes an FPGA solution slower than an ASIC design. Bit-oriented computational units make them unnecessarily inefficient for implementing tasks that are generally word-oriented. And finally, in large volumes, FPGAs tend to be more expensive per unit due to their lower transistor density. To combat these problems, researchers are now exploiting the unique advantage that FPGAs exhibit over ASICs: reconfigurability. By customizing the FPGA to the task at hand, as the application executes, it is hoped that the cost-performance product of an FPGA system can be shown to be a better solution than a system implemented by a collection of custom ASICs. Such a system is called a Configurable Computing Machine (CCM). Many aspects of the design of the FPGAs available today hinder the exploration of this field. This thesis addresses many of these problems and presents the embodiment of those solutions in the Colt CCM. By offering word grain reconfiguration and the ability to partially reconfigure at computational element resolution, the Colt can offer higher effective utilization over traditional FPGAs. Further, the majority of the pins of the Colt can be used for both normal I/O and for chip reconfiguration. This provides higher reconfiguration bandwidth contrasted with the low percentage of pins used for reconfiguration of FPGAs. Finally, Colt uses a distributed reconfiguration mechanism called Wormhole Run-Time Reconfiguration (RTR) that allows multiple data ports to simultaneously program different sections of the chip independently. Used as the primary example of Wormhole RTR in the patent application, Colt is the first system to employ this computing paradigm.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartetd.pdfen_US
dc.rightsI hereby grant to Virginia Tech or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University Libraries in all forms of media, now or hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en_US
dc.subjectwormhole run-time reconfigurationen_US
dc.subjectDSPen_US
dc.subjectdata flowen_US
dc.subjectVLSIen_US
dc.subjectFPGAen_US
dc.subject.lccLD5655.V856 1997.B588en_US
dc.titleWormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing Systemen_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
thesis.degree.namePhDen_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberMidkiff, Scott F.en_US
dc.contributor.committeememberDavis, Nathaniel J. IVen_US
dc.contributor.committeememberAbbott, A. Lynnen_US
dc.contributor.committeememberRibbens, Calvin J.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-38419290973280/en_US
dc.date.sdate1998-07-11en_US
dc.date.rdate1997-01-23
dc.date.adate1997-01-23en_US


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