Residual Stress Effects on Power Slump and Wafer Breakage in GaAs MESFETs

Abstract

The objectives of this investigation are to develop a precise, non-destructive single crystal stress measurement technique, develop a model to explain the phenomenon known as 3power slump2, and investigate the role of device processing on wafer breakage. All three objectives were successfully met. The single crystal stress technique uses a least squares analysis of X-ray diffraction data to calculate the full stress tensor. In this way, precise non-destructive stress measurements can be made with known error bars. Rocking curve analysis, stress gradient corrections, and a data reliability technique were implemented to ensure that the stress data are correct. A theory was developed to explain 3power slump2, which is a rapid decrease in the amplifying properties of microwave amplifier circuits during operation. The model explains that for the particular geometry and bias configuration of the devices studied in this research, power slump is linearly related to shear stress at values of less than 90 MPa. The microscopic explanation of power slump is that radiation enhanced dislocation glide increases the kink concentration, thereby increasing the generation center concentration in the active region of the device. These generation centers increase the total gate current, leading to a decrease in the amplifying properties of the device. Passivation layer processing has been shown to both reduce the fracture strength and increase the residual stress in GaAs wafers, making them more susceptible to wafer breakage. Bare wafers are found to have higher fracture strength than passivated wafers. Bare wafers are also found to contain less residual stress than SiON passivated wafers, which, in turn, are found to have less stress than SiN passivated wafers. Topographic imaging suggests that SiN passivated wafers have larger flaws than SiON passivated wafers, and that the distribution of flaw size among SiN passivated wafers is wider than the distribution of flaws in SiON passivated wafers. These flaws are believed to lead to breakage of the device during processing, resulting in low fabrication yield. Both the power slump model and the wafer breakage data show that these phenomena are dependent on residual stress developed in the substrate during device fabrication. Reduction of process-induced residual stress should therefore simultaneously decrease wafer breakage rates and reduce power slump during device fabrication and operation.