Show simple item record

dc.contributor.authorAlmajdoub, Salahuddin A.en
dc.date.accessioned2014-03-14T20:22:06Zen
dc.date.available2014-03-14T20:22:06Zen
dc.date.issued1996-07-01en
dc.identifier.otheretd-522014589642481en
dc.identifier.urihttp://hdl.handle.net/10919/30574en
dc.description.abstractPhysical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare faults, the design process utilizes a new parameter called the fault index. The fault index for a particular fault is the probability of occurrence of the fault divided by the testability of the fault. Faults with the highest fault indices are considered the worst faults and are targeted by the PDFT design process to eliminate them or reduce their probability of occurrence. An implementation of the PDFT design process is constructed using several new tools in addition to other "off-the-shelf" tools. The first tool developed in this work is a testability measure tool for bridging faults. Two other tools are developed to eliminate or reduce the probability of occurrence of bridging faults with high fault indices. The row enhancer targets faults inside the logic elements of the circuit, while the channel enhancer targets faults inside the routing part of the circuit. To demonstrate the capabilities and test the eff ectiveness of the PDFT design process, this work conducts an experiment which includes designing three CMOS circuits from the ISCAS 1985 benchmark circuits. Several layouts are generated for every circuit. Every layout, except the rst one, utilizes information from the previous layout to minimize the probability of occurrence for faults with high fault indices. Experimental results show that the PDFT design process successfully achieves two goals of PDFT, providing layouts with fewer faults and minimizing the probability of occurrence of hard-to-test faults. Improvement in the total fault index was about 40 percent in some cases, while improvement in total critical area was about 30 percent in some cases. However, virtually all the improvements came from using the row enhancer; the channel enhancer provided only marginal improvements.en
dc.publisherVirginia Techen
dc.relation.haspartetd.pdfen
dc.relation.haspartalmajdoub.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectBridging Faultsen
dc.subjectThe Labour Partyen
dc.subjectStructure and Agencyen
dc.subjectIDDQ Testingen
dc.subjectElectoral Performanceen
dc.subjectPhysical Design for Testabilityen
dc.subject.lccLD5655.V856 1996.A462en
dc.titleA Design Methodology for Physical Design for Testabilityen
dc.typeDissertationen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreePh. D.en
thesis.degree.namePh. D.en
thesis.degree.leveldoctoralen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical and Computer Engineeringen
dc.contributor.committeechairTaylor, Charles L.en
dc.contributor.committeechairMidkiff, Scott F.en
dc.contributor.committeememberDavis, Rebecca H.en
dc.contributor.committeememberWhite, Stephen K.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberSherali, Hanif D.en
dc.contributor.committeememberElshabini-Riad, Aicha A.en
dc.contributor.committeememberTront, Joseph G.en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-522014589642481/en
dc.date.sdate1998-07-11en
dc.date.rdate1996-07-01en
dc.date.adate1996-07-01en


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record