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dc.contributor.authorLostetter, Alexander B.en_US
dc.date.accessioned2014-03-14T20:30:30Z
dc.date.available2014-03-14T20:30:30Z
dc.date.issued1998-05-12en_US
dc.identifier.otheretd-011199-231941en_US
dc.identifier.urihttp://hdl.handle.net/10919/30909
dc.description.abstractHigh power circuits, those involving high levels of voltages and currents to produce several kilowatts of power, would possess an optimized efficiency when driven at high frequencies (on the order of MHz). Such an approach would greatly reduce the size of capacitive and magnetic components, and thus ultimately reduce the cost of the power electronic circuits. The problem with this strategy in conventional packaging, however, is that at high frequencies, interconnects between the power devices on one board (such as Power MOSFETs or IGBTs) and components on another board (such as the coasting diodes) suffer from severe parasitic effects, thus affecting the overall electrical performance of the system. A conceivable solution to this problem is the design and construction of a power electronics module which would incorporate all power devices and supporting circuitry into one very simple and compact module. Such an approach would reduce interconnect inductances (thus reducing costly parasitic effects), increase system efficiency and electrical performance, produce a standardization for power electronic modules, and through this standardization, lower overall industry-wide system costs and increase power electronic system reliability. This technology would prove especially valuable for power electronics in industry, where prevalent power systems such as half bridge or full bridge converters would benefit greatly from the large reduction of inductances which currently exist between separate bridge legs. This thesis will discuss a novel multilayer approach towards the described issues. A power module has been designed and fabricated which contains one metallization power layer for the power devices, and a second metallization control layer for the low power signal components. The two layers are separated by a dielectric layer which serves as an electrical separation and as a physical spacer. In addition, issues have been addressed towards optimal physical layout and construction (with regards to thermal dissipation), materials comparisons have been made, and thermal simulations and experimental verifications performed. Issues relating to standardized power electronic module design and the efforts of this researcher at the Microelectronics Laboratories at Virginia Polytechnic Institute and State University to contribute to this quickly evolving field will be discussed. Such topics as power electronic module design, control and driver circuitry design, material issues, and thermal issues will be discussed.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartTHESIS_A.PDFen_US
dc.rightsI hereby grant to Virginia Tech or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University Libraries in all forms of media, now or hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en_US
dc.subjectpower electronicsen_US
dc.subjectthermal analysisen_US
dc.subjectpackagingen_US
dc.titleMiniaturization, Packaging, and Thermal Analysis of Power Electronics Modulesen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairElshabini-Riad, Aicha A.en_US
dc.contributor.committeememberBesieris, Ioannis M.en_US
dc.contributor.committeememberRaman, Sanjayen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-011199-231941/en_US
dc.date.sdate1999-01-11en_US
dc.date.rdate1999-02-08
dc.date.adate1999-02-08en_US


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