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dc.contributor.authorKim, Jinaen_US
dc.date.accessioned2014-03-14T20:30:51Z
dc.date.available2014-03-14T20:30:51Z
dc.date.issued2003-01-16en_US
dc.identifier.otheretd-01172003-111046en_US
dc.identifier.urihttp://hdl.handle.net/10919/30972
dc.description.abstractA rake receiver, which resolves multipath signals corrupted by a fading channel, is the most complex and power consuming block of a modem chip. Therefore, it is essential to design a rake receiver be efficient in hardware and power. We investigated a design of a rake receiver for the WCDMA (Wideband Code Division Multiple Access) system, which is a third generation wireless communication system. Our rake receiver design is targeted for mobile units, in which low-power consumption is highly important. We made judicious judgments throughout our design process to reduce the overall circuit complexity by trading with the performance. The reduction of the circuit complexity results in low power dissipation for our rake receiver. As the first step in the design of a rake receiver, we generated a software prototype in MATLAB. The prototype included a transmitter and a multipath Rayleigh fading channel, as well as a rake receiver with four fingers. Using the software prototype, we verified the functionality of all blocks of our rake receiver, estimated the performance in terms of bit error rate, and investigated trade-offs between hardware complexity and performance. After the verification and design trade-offs were completed, we manually developed a rake receiver at the RT (Register Transfer) level in VHDL. We proposed and incorporated several schemes in the RT level design to enhance the performance of our rake receiver. As the final step, the RT level design was synthesized to gate level circuits targeting TSMC 0.18 mm CMOS technology under the supply voltage of 1.8 V. We estimated the performance of our rake receiver in area and power dissipation. Our experimental results indicate that the total power dissipation for our rake receiver is 56 mW and the equivalent NAND2 circuit complexity is 983,482. We believe that the performance of our rake receiver is quite satisfactory.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartjnkim_thesis.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectPower Dissipationen_US
dc.subjectCircuit complexityen_US
dc.subjectMultipathen_US
dc.subjectRake Receiveren_US
dc.subjectWCDMAen_US
dc.titleArea and Power Conscious Rake Receiver Design for Third Generation WCDMA Systemsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairHa, Dong Samen_US
dc.contributor.committeememberArmstrong, James R.en_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-01172003-111046/en_US
dc.date.sdate2003-01-17en_US
dc.date.rdate2004-01-17
dc.date.adate2003-01-17en_US


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