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dc.contributor.authorKim, Jinaen
dc.date.accessioned2014-03-14T20:30:51Zen
dc.date.available2014-03-14T20:30:51Zen
dc.date.issued2003-01-16en
dc.identifier.otheretd-01172003-111046en
dc.identifier.urihttp://hdl.handle.net/10919/30972en
dc.description.abstractA rake receiver, which resolves multipath signals corrupted by a fading channel, is the most complex and power consuming block of a modem chip. Therefore, it is essential to design a rake receiver be efficient in hardware and power. We investigated a design of a rake receiver for the WCDMA (Wideband Code Division Multiple Access) system, which is a third generation wireless communication system. Our rake receiver design is targeted for mobile units, in which low-power consumption is highly important. We made judicious judgments throughout our design process to reduce the overall circuit complexity by trading with the performance. The reduction of the circuit complexity results in low power dissipation for our rake receiver. As the first step in the design of a rake receiver, we generated a software prototype in MATLAB. The prototype included a transmitter and a multipath Rayleigh fading channel, as well as a rake receiver with four fingers. Using the software prototype, we verified the functionality of all blocks of our rake receiver, estimated the performance in terms of bit error rate, and investigated trade-offs between hardware complexity and performance. After the verification and design trade-offs were completed, we manually developed a rake receiver at the RT (Register Transfer) level in VHDL. We proposed and incorporated several schemes in the RT level design to enhance the performance of our rake receiver. As the final step, the RT level design was synthesized to gate level circuits targeting TSMC 0.18 mm CMOS technology under the supply voltage of 1.8 V. We estimated the performance of our rake receiver in area and power dissipation. Our experimental results indicate that the total power dissipation for our rake receiver is 56 mW and the equivalent NAND2 circuit complexity is 983,482. We believe that the performance of our rake receiver is quite satisfactory.en
dc.publisherVirginia Techen
dc.relation.haspartjnkim_thesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectPower Dissipationen
dc.subjectCircuit complexityen
dc.subjectMultipathen
dc.subjectRake Receiveren
dc.subjectWCDMAen
dc.titleArea and Power Conscious Rake Receiver Design for Third Generation WCDMA Systemsen
dc.typeThesisen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical and Computer Engineeringen
dc.contributor.committeechairHa, Dong Samen
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.committeememberTront, Joseph G.en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-01172003-111046/en
dc.date.sdate2003-01-17en
dc.date.rdate2004-01-17en
dc.date.adate2003-01-17en


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