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dc.contributor.authorJayaram, Vinay B.en
dc.date.accessioned2014-03-14T20:31:32Zen
dc.date.available2014-03-14T20:31:32Zen
dc.date.issued2003-01-29en
dc.identifier.otheretd-02062003-145930en
dc.identifier.urihttp://hdl.handle.net/10919/31146en
dc.description.abstractThe presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are associated with pattern generation and application. Our work focuses on the implementation and comparison of these transition fault testing techniques on multiple industrial ASIC designs. In this thesis, we present results from multiple designs and compare the two techniques with respect to test coverage, pattern volume and pattern generation time. For both methods, we discuss the effects of multiple clock domains, tester hardware considerations, false and multi-cycle paths and the implications of using a low cost tester. We then consider the implications of pattern volume on testing both stuck-at and transition faults and the effects of using transition fault patterns to test stuck-at faults. Finally, we present results from our analysis on switching activity of nets in the design, while executing transition fault patterns.en
dc.publisherVirginia Techen
dc.relation.haspartetd.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectbroad-sideen
dc.subjectATPGen
dc.subjecttest coverageen
dc.subjectskewed loaden
dc.subjecttransition faultsen
dc.subjectpattern volumeen
dc.titleExperimental Study of Scan Based Transition Fault Testing Techniquesen
dc.typeThesisen
dc.contributor.departmentElectrical and Computer Engineeringen
dc.description.degreeMaster of Scienceen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelmastersen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.disciplineElectrical and Computer Engineeringen
dc.contributor.committeechairHsiao, Michael S.en
dc.contributor.committeememberBaker, James M. Jr.en
dc.contributor.committeememberShukla, Sandeep K.en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-02062003-145930/en
dc.date.sdate2003-02-06en
dc.date.rdate2004-02-19en
dc.date.adate2003-02-19en


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