A Synchronous Distributed Digital Control Architecture for High Power Converters
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This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller.
- Masters Theses