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Intra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchies
The use of asymmetric multi-core processors with on-chip computational
accelerators is becoming common in a variety of environments ranging from
scientific computing to enterprise applications. The focus of current research
has been on making efficient use of individual systems, and porting
applications to asymmetric processors. The use of these asymmetric processors,
like the Cell processor, in a cluster setting is the inspiration for the Cell
Connector framework presented in this thesis. Cell Connector adopts a streaming
approach for providing data to compute nodes with high computing potential but limited
memory resources. Instead of dividing very large data sets once among computation
resources, Cell Connector slices, distributes, and collects work units off of a master data
held by a single large memory machine. Using this methodology, Cell Connector is
able to maximize the use of limited resources and produces results that are up to
63.3\% better compared to standard non-streaming approaches.