Show simple item record

dc.contributor.authorRose, Benjamin Aaronen_US
dc.date.accessioned2014-03-14T20:37:01Z
dc.date.available2014-03-14T20:37:01Z
dc.date.issued2009-05-12en_US
dc.identifier.otheretd-05152009-170830en_US
dc.identifier.urihttp://hdl.handle.net/10919/32824
dc.description.abstractThe use of asymmetric multi-core processors with on-chip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise applications. The focus of current research has been on making efficient use of individual systems, and porting applications to asymmetric processors. The use of these asymmetric processors, like the Cell processor, in a cluster setting is the inspiration for the Cell Connector framework presented in this thesis. Cell Connector adopts a streaming approach for providing data to compute nodes with high computing potential but limited memory resources. Instead of dividing very large data sets once among computation resources, Cell Connector slices, distributes, and collects work units off of a master data held by a single large memory machine. Using this methodology, Cell Connector is able to maximize the use of limited resources and produces results that are up to 63.3\% better compared to standard non-streaming approaches.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartmain.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectCell BEen_US
dc.subjectmulticoreen_US
dc.subjectclusteren_US
dc.titleIntra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchiesen_US
dc.typeThesisen_US
dc.contributor.departmentComputer Scienceen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineComputer Scienceen_US
dc.contributor.committeechairNikolopoulos, Dimitrios S.en_US
dc.contributor.committeememberButt, Ali R. A.en_US
dc.contributor.committeememberLowenthal, David K.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-05152009-170830/en_US
dc.date.sdate2009-05-15en_US
dc.date.rdate2009-06-10
dc.date.adate2009-06-10en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record