Show simple item record

dc.contributor.authorJemibewon, Abayomi Oluwaseyien_US
dc.date.accessioned2014-03-14T20:41:40Z
dc.date.available2014-03-14T20:41:40Z
dc.date.issued2000-07-07en_US
dc.identifier.otheretd-07202000-11180005en_US
dc.identifier.urihttp://hdl.handle.net/10919/34072
dc.description.abstract

Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge.

In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion.

en_US
dc.publisherVirginia Techen_US
dc.relation.haspartthesis.pdfen_US
dc.rightsI hereby grant to Virginia Tech or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University Libraries in all forms of media, now or hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en_US
dc.subjectVariable resolutionen_US
dc.subjectAnalog-to-digital converteren_US
dc.subjectTurbo Codesen_US
dc.titleA Smart Implementation of Turbo Decoding for Improved Power Efficiencyen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairWoerner, Brain D.en_US
dc.contributor.committeememberDavis, William A.en_US
dc.contributor.committeememberReed, Jeffrey Hughen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07202000-11180005/en_US
dc.date.sdate2000-07-20en_US
dc.date.rdate2001-07-20
dc.date.adate2000-07-20en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record