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dc.contributor.authorGold, Brianen_US
dc.date.accessioned2014-03-14T20:41:52Z
dc.date.available2014-03-14T20:41:52Z
dc.date.issued2003-07-23en_US
dc.identifier.otheretd-07242003-134147en_US
dc.identifier.urihttp://hdl.handle.net/10919/34137
dc.description.abstractSeveral trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications. The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects. This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartbtgthesis.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectareaen_US
dc.subjectvirtual channelsen_US
dc.subjectSCMPen_US
dc.subjectpoweren_US
dc.subjectnetworken_US
dc.subjectrouteren_US
dc.subjectcrossbar switchen_US
dc.subjectsingle chip computeren_US
dc.subjectmessage passingen_US
dc.subjectsystem on chipen_US
dc.titleBalancing Performance, Area, and Power in an On-Chip Networken_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairBaker, James M. Jr.en_US
dc.contributor.committeememberMichael S, Hsiaoen_US
dc.contributor.committeememberJones, Mark T.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07242003-134147/en_US
dc.date.sdate2003-07-24en_US
dc.date.rdate2003-08-06
dc.date.adate2003-08-06en_US


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