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dc.contributor.authorSirpatil, Brijeshen_US
dc.date.accessioned2014-03-14T20:42:13Z
dc.date.available2014-03-14T20:42:13Z
dc.date.issued2002-07-26en_US
dc.identifier.otheretd-07302002-104102en_US
dc.identifier.urihttp://hdl.handle.net/10919/34255
dc.description.abstractTechnological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SOC). In SOC designs all the functionality of a system is put inside a single chip, leading to increased performance, reduced power consumption, lower costs, and reduced size. SOC design brings with it new challenges and difficulties, however. The designs are now large, complicated and involve both software and hardware components. The designs have to be modeled at a high level of abstraction before partitioning into hardware and software components for final implementation. SystemC is a system level modeling language useful for System On a Chip design. It provides various features to perform system level modeling and simulation, which are missing in the generic HDL's such as VHDL and Verilog. The hardware portion of the SystemC models can be synthesized into hardware using commercial tools . The software portion can be rewritten as embedded software for the target processor. The aim of this thesis is to explore the SOC design process and to define methods for software synthesis of SystemC models. Software synthesis involves translation of SystemC models into code that is suitable for execution on an embedded processor. A simple scheduler that replaces the SystemC simulation kernel is proposed. This scheduler allows SystemC models to be executed directly as embedded software without the need for extensive modification or translation. Application of this process to the development of a GSM speech processing system, including the translation of part of the SystemC model into software that will execute on an embedded processor, is shown and the results are presented.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartthesis.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectSystemCen_US
dc.subjectSoftware Synthesisen_US
dc.subjectEmbedded softwareen_US
dc.subjectGSMen_US
dc.titleSoftware Synthesis of SystemC Modelsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairBaker, James M. Jr.en_US
dc.contributor.committeememberGray, Festus Gailen_US
dc.contributor.committeememberArmstrong, James R.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07302002-104102/en_US
dc.date.sdate2002-07-30en_US
dc.date.rdate2003-08-01
dc.date.adate2002-08-01en_US


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