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dc.contributor.authorSinha, Ambuj Sudhiren_US
dc.date.accessioned2014-03-14T20:43:09Z
dc.date.available2014-03-14T20:43:09Z
dc.date.issued2011-08-05en_US
dc.identifier.otheretd-08102011-151100en_US
dc.identifier.urihttp://hdl.handle.net/10919/34465
dc.description.abstractSide Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is focussed towards developing countermeasures to side channel attacks. In this thesis, we address two challenges that are an inherent part of the efficient implementation of SCA countermeasures. While designing a system, design choices made for enhancing the efficiency or performance of the system can also affect the side channel security of the system. The first challenge is that the effect of different design choices on the side channel resistance of a system is currently not well understood. It is important to understand these effects in order to develop systems that are both secure and efficient. A second problem with incorporating SCA countermeasures is the increased design complexity. It is often difficult and time consuming to integrate an SCA countermeasure in a larger system. In this thesis, we explore that above mentioned problems from the point of view of developing embedded software that is resistant to power based side channel attacks. Our first work is an evaluation of different software AES implementations, from the perspective of side channel resistance, that shows the effect of design choices on the security and performance of the implementation. Next we present work that identifies the problems that arise while designing software for a particular type of SCA resistant architecture - the Virtual Secure Circuit. We provide a solution in terms of a methodology that can be used for developing software for such a system - and also demonstrate that this methodology can be conveniently automated - leading to swifter and easier software development for side channel resistant designs.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartSinha_AS_T_2011.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectBitslice Cryptographyen_US
dc.subjectSide Channel Attacksen_US
dc.subjectVirtual Secure Circuiten_US
dc.subjectSecure Embedded Systemsen_US
dc.subjectSide-channel Countermeasuresen_US
dc.titleDesign Techniques for Side-channel Resistant Embedded Softwareen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairSchaumont, Patrick Roberten_US
dc.contributor.committeememberShukla, Sandeep K.en_US
dc.contributor.committeememberHsiao, Michael S.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-08102011-151100/en_US
dc.date.sdate2011-08-10en_US
dc.date.rdate2011-08-25
dc.date.adate2011-08-25en_US


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