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dc.contributor.authorMarballie, Gladstone Washingtonen_US
dc.date.accessioned2014-03-14T20:46:45Z
dc.date.available2014-03-14T20:46:45Z
dc.date.issued2010-10-06en_US
dc.identifier.otheretd-10162010-185837en_US
dc.identifier.urihttp://hdl.handle.net/10919/35409
dc.description.abstractThe Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish physical layer communications using the received signalâ s profile. The current implementation is able to identify signals including AM, FM, MPSK, QAM, MFSK, and OFDM. The system is constructed to run on a Universal Software Radio Peripheral (USRP) with the GNU Radio software toolkit and also runs on an Anritsuâ ¢ signal analyzer. In both prototypes, the UCS system runs on a host computerâ s General Purpose Processor (GPP) and is constructed in Matlabâ ¢. The aim is to then create a portable and standalone version of the UCS system as an intermediate step towards building a future commercial implementation. This application and particular implementation aims to run on a Lyrtech SFF SDR platform and uses its FPGA and DSP modules for implementation. This platform is one of the more advanced SDR platforms available, and the aim is to develop parts of the UCS system to run on this platform. The aim is to eventually develop the complete UCS cognitive radio system on the Lyrtech SFF SDR platform that can act as a standalone portable cognitive radio system. The modules created and implanted/implemented on the SDR hardware are the Bandwidth Estimation, and Symbol Timing & Coarse Classification modules. This is the system decision path towards classification, synchronization, and demodulation of digital phase modulated signals (QAM and MPSK signal types) and also analog signals. The Digital Receiver Module (DRM) is implemented on the FPGA and takes care of all the digital down conversions, mixing, decimation, and low pass filtering. The FPGA is connected to the DSP module via a bus subsystem where the DSP receives real-time base-band complex IQ samples for further signal processing. The main UCS algorithm runs on the platformâ s DSP and is compiled from executable embedded C-code. Therefore, this system can then be implemented on virtually any setup that has an RF front end, digital receiver module, and processing module that will execute floating and fixed point C-code with minor changes.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartMarballie_GW_T_2010.pdfen_US
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectFPGAen_US
dc.subjectSignal Classificationen_US
dc.subjectSymbol Timingen_US
dc.subjectDSPen_US
dc.subjectSDRen_US
dc.subjectCognitive Radioen_US
dc.titleSymbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platformen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairBostian, Charles W.en_US
dc.contributor.committeememberPatterson, Cameron D.en_US
dc.contributor.committeememberPratt, Timothy J.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-10162010-185837/en_US
dc.date.sdate2010-10-16en_US
dc.date.rdate2010-11-01
dc.date.adate2010-11-01en_US


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