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dc.contributor.authorAsthana, Rohit Mohanen_US
dc.date.accessioned2014-03-14T20:50:44Z
dc.date.available2014-03-14T20:50:44Z
dc.date.issued2010-12-14en_US
dc.identifier.otheretd-12232010-123433en_US
dc.identifier.urihttp://hdl.handle.net/10919/36428
dc.description.abstractThe ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out dierent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between different components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartAsthana_RM_T_2010.pdfen_US
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to Virginia Tech or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectHigh-Level Synthesisen_US
dc.subjectFPGAsen_US
dc.subjectModels of Computation (MoC)en_US
dc.subjectCommunicating Sequential Processes (CSP)en_US
dc.subjectAutocode Generationen_US
dc.titleHigh-Level CSP Model Compiler for FPGAsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberSchaumont, Patrick Roberten_US
dc.contributor.committeememberPlassmann, Paul E.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-12232010-123433/en_US
dc.date.sdate2010-12-23en_US
dc.date.rdate2011-01-19
dc.date.adate2011-01-19en_US


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