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dc.contributor.authorKahne, Brian C.en_US
dc.date.accessioned2014-03-14T20:50:59Z
dc.date.available2014-03-14T20:50:59Z
dc.date.issued1997-05-14en_US
dc.identifier.otheretd-1629131549741341en_US
dc.identifier.urihttp://hdl.handle.net/10919/36521
dc.description.abstractConfigurable Computing is a technology which attempts to increase computational power by customizing the computational platform to the specific problem at hand. An experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, which can tunnel through the chip creating a series of interconnected pipelines. The Colt/Stallion project at Virginia Tech implements this computing model into integrated circuits. In order to create applications for this platform, a compiler is needed which can convert a human readable description of an algorithm into the sequences of configuration information understood by the chip itself. This thesis covers two compilers which perform this task. The first compiler, Tier1, requires a programmer to explicitly describe placement and routing inside of the chip. This could be considered equivalent to an assembler for a traditional microprocessor. The second compiler, Tier2, allows the user to express a problem as a dataflow graph. Actual placing and routing of this graph onto the physical hardware is taken care of through the use of a genetic algorithm. A description of the two languages is presented, followed by example applications. In addition, experimental results are included which examine the behavior of the genetic algorithm and how alterations to various genetic operator probabilities affects performance.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartetd.pdfen_US
dc.rightsI hereby grant to Virginia Tech or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University Libraries in all forms of media, now or hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en_US
dc.subjectplacementen_US
dc.subjectgenetic algorithmen_US
dc.subjectroutingen_US
dc.subjectconfigurable computing wormholeen_US
dc.subjectrun-time reconfigurationen_US
dc.titleA Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing Systemen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberNunnally, Charles E.en_US
dc.contributor.committeememberArmstrong, James R.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-1629131549741341/en_US
dc.date.sdate1998-07-17en_US
dc.date.rdate1997-05-14
dc.date.adate1997-05-14en_US


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