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dc.contributor.authorMusgrove, Mark D.en_US
dc.date.accessioned2014-03-14T20:51:42Z
dc.date.available2014-03-14T20:51:42Z
dc.date.issued1996-11-07en_US
dc.identifier.otheretd-4941511109613150en_US
dc.identifier.urihttp://hdl.handle.net/10919/36756
dc.description.abstractThe growth of high performance computing to date can largely be attributed to continuing breakthroughs in materials and manufacturing.In order to increase computing capacity beyond these physical bounds, new computing paradigms must be developed that make more efficient use of existing manufacturing technologies. Custom Computing Machines (CCMs) are an emerging class of computers that offer promising possibilities for future high-performance computational needs. With the increasing popularity of the run-time reconfigurable (RTR) concept in the CCM community, questions have arisen as to what computational device should be at the heart of an RTR platform. Currently the preferred device, and really the only practical device, has been the RAM-based Field-Programmable Gate Array (FPGA). Unfortunately, for applications that require high performance, FPGAs are limited by their narrow data path and small computational density. The Colt integrated circuit has been designed from the start to be the computational processing element in an RTR platform. Colt is an RTR data-flow processor array with a course-grain architecture (16-bit data path). This thesis covers the VLSI implementation and verification of the Colt integrated circuit, including the approach and methods necessary to make a functionally working integrated circuit.en_US
dc.publisherVirginia Techen_US
dc.relation.haspartmusgrove.pdfen_US
dc.relation.haspartetd.pdfen_US
dc.rightsI hereby grant to Virginia Tech or its agents the right to archive and to make available my thesis or dissertation in whole or in part in the University Libraries in all forms of media, now or hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en_US
dc.subjectVLSIen_US
dc.subjectrun-time reconfigurableen_US
dc.subjectconfigurable computingen_US
dc.subjectdata flowen_US
dc.subjectFPGAen_US
dc.subjectDSPen_US
dc.titleVLSI Implementation of a Run-time Reconfigurable Custom Computing Integrated Circuiten_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberWoerner, Brian D.en_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-4941511109613150/en_US
dc.date.sdate1998-07-19en_US
dc.date.rdate1996-11-07
dc.date.adate1996-11-07en_US


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