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dc.contributor.authorCho, Chang H.en_US
dc.date.accessioned2014-03-14T21:14:11Z
dc.date.available2014-03-14T21:14:11Z
dc.date.issued1994-02-08en_US
dc.identifier.otheretd-06062008-170406en_US
dc.identifier.urihttp://hdl.handle.net/10919/38405
dc.description.abstractsee documenten_US
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V856_1994.C56.pdfen_US
dc.subjectIntegrated circuitsen_US
dc.subject.lccLD5655.V856 1994.C56en_US
dc.titleA formal model for behavioral test generationen_US
dc.typeDissertationen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreePh. D.en_US
thesis.degree.namePh. D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.committeechairArmstrong, James R.en_US
dc.contributor.committeememberBrown, Ezra A.en_US
dc.contributor.committeememberHa, Dong Samen_US
dc.contributor.committeememberGray, Festus Gailen_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06062008-170406/en_US
dc.date.sdate2008-06-06en_US
dc.date.rdate2008-06-06
dc.date.adate2008-06-06en_US


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