Interfacing VHDL performance models to algorithm partitioning tools
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Performance modeling is widely used to efficiently and rapidly assess the ability of multiprocessor architectures to effectively execute a given algorithm. In a typical design environment, VHD L performance models of hardware components are interconnected to form structural models of the target multiprocessor architectures. Algorithm features are described in application specific tools. Other automated tools partition the software among the various processors. Performance models evaluate the system performance. Since several iterations may be needed before a suitable configuration is obtained, a set of tools that directly interfaces the VHDL performance models to the algorithm partitioning tools will significantly reduce the time and effort needed to prepare the various models. In order to develop the interface tools, it is essential to determine the information that needs to be interchanged between the two systems. The primary goals of this thesis are to study the various models, determine the information that needs to be exchanged, and to develop tools to automatically extract the desired information from each model.
- Masters Theses