Virginia Tech
    • Log in
    View Item 
    •   VTechWorks Home
    • ETDs: Virginia Tech Electronic Theses and Dissertations
    • Masters Theses
    • View Item
    •   VTechWorks Home
    • ETDs: Virginia Tech Electronic Theses and Dissertations
    • Masters Theses
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Methodology for structured VHDL model development

    Thumbnail
    View/Open
    LD5655.V855_1995.G866.pdf (3.098Mb)
    Downloads: 111
    Date
    1995-04-05
    Author
    Gummadi, Ram
    Metadata
    Show full item record
    Abstract

    The Rapid Prototyping of Application Specific Signal Processors (RASSP) program seeks an improvement in the time required to take a design from concept to fielded prototype or to upgrade an existing design, with similar improvements in design quality and life cycle cost. The term Rapid System Prototyping signifies the need to develop systems in significantly less time or with significantly less effort, and thus provides a solution to the main problem facing the design community. Entire systems are synthesized from models in hardware description languages (HDLs).

    The goal of this thesis is to provide a methodology for rapidly creating a database, that can be reused thus decreasing design cost and time for both current and future projects. To demonstrate the methodology, this thesis describes the development of VHDL primitives supporting digital signal processing (DSP) and image processing operations for two of the RASSP specific applications: 1) Synthetic aperture radar image processor (SAR) and 2) Automatic target recognition (ATR) image processing algorithm. Different techniques are investigated to populate these VHDL libraries using commercial tools. The thesis proposes techniques for solving some problems related to the use of commercial tools to generate VHDL code. It includes a full implementation of the SAR processor algorithm developed from DSP primitives.

    URI
    http://hdl.handle.net/10919/41730
    Collections
    • Masters Theses [19662]

    If you believe that any material in VTechWorks should be removed, please see our policy and procedure for Requesting that Material be Amended or Removed. All takedown requests will be promptly acknowledged and investigated.

    Virginia Tech | University Libraries | Contact Us
     

     

    VTechWorks

    AboutPoliciesHelp

    Browse

    All of VTechWorksCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

    My Account

    Log inRegister

    Statistics

    View Usage Statistics

    If you believe that any material in VTechWorks should be removed, please see our policy and procedure for Requesting that Material be Amended or Removed. All takedown requests will be promptly acknowledged and investigated.

    Virginia Tech | University Libraries | Contact Us