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dc.contributor.authorGriffin, Glennen_US
dc.date.accessioned2014-03-14T21:34:56Z
dc.date.available2014-03-14T21:34:56Z
dc.date.issued1993-04-05en_US
dc.identifier.otheretd-04272010-020102en_US
dc.identifier.urihttp://hdl.handle.net/10919/42309
dc.description.abstractThe ability to extract higher level information from a circuit netlist is useful for VLSI layout verification. An extracted gate level description may be used as input to a gate level simulator for analysis or alternatively may be used as input to a rule-based expert system that performs verification checking at a higher level of abstraction. As a VLSI design evolves it is continually checked for correctness. This implies that the extraction of higher level information is a recurring activity and should be performed as efficiently as possible. This paper describes an alternative method that uses intelligence to quicken the extraction process and compares this method's performance to a more common method.en_US
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V851_1993.G754.pdfen_US
dc.subjectIntegrated circuitsen_US
dc.subject.lccLD5655.V851 1993.G754en_US
dc.titleIntelligent circuit recognition for VLSI layout verificationen_US
dc.typeMaster’s projecten_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.committeechairTront, Joseph G.en_US
dc.contributor.committeememberMidkiff, Scott F.en_US
dc.contributor.committeememberCyre, Walling R.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-04272010-020102/en_US
dc.date.sdate2010-04-27en_US
dc.date.rdate2010-04-27
dc.date.adate2010-04-27en_US


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