Show simple item record

dc.contributor.authorO'Neill, Michael Douglasen_US
dc.date.accessioned2014-03-14T21:38:23Z
dc.date.available2014-03-14T21:38:23Z
dc.date.issued1988en_US
dc.identifier.otheretd-06122010-020415en_US
dc.identifier.urihttp://hdl.handle.net/10919/43262
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V855_1988.O645.pdfen_US
dc.subjectIntegrated circuitsen_US
dc.subject.lccLD5655.V855 1988.O645en_US
dc.titleAn improved chip-level test generation algorithmen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06122010-020415/en_US
dc.date.sdate2010-06-12en_US
dc.date.rdate2010-06-12
dc.date.adate2010-06-12en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record