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dc.contributor.authorBurnette, David G.en_US
dc.date.accessioned2014-03-14T21:38:55Z
dc.date.available2014-03-14T21:38:55Z
dc.date.issued1988-05-14en_US
dc.identifier.otheretd-06222010-020057en_US
dc.identifier.urihttp://hdl.handle.net/10919/43381
dc.description.abstractThis paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers. *VHDLCad is a trademark of David G. Burnette. **Copyright 1988 by David G. Burnette. All rights reserveden_US
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V855_1988.B8745.pdfen_US
dc.subjectElectronic circuitsen_US
dc.subject.lccLD5655.V855 1988.B8745en_US
dc.titleA graphical representation for VHDL modelsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.committeechairArmstrong, James R.en_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.contributor.committeememberHa, Dong Samen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-06222010-020057/en_US
dc.date.sdate2010-06-22en_US
dc.date.rdate2010-06-22
dc.date.adate2010-06-22en_US


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