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dc.contributor.authorChu, Ming-Cheungen_US
dc.date.accessioned2014-03-14T21:46:52Z
dc.date.available2014-03-14T21:46:52Z
dc.date.issued1992-07-06en_US
dc.identifier.otheretd-10062009-020040en_US
dc.identifier.urihttp://hdl.handle.net/10919/45005
dc.description.abstractsee documenten_US
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V855_1992.C58.pdfen_US
dc.subjectLogic circuits.en_US
dc.subject.lccLD5655.V855 1992.C58en_US
dc.titleHazard detection with VHDL in combinational logic circuits with fixed delaysen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
dc.contributor.committeechairArmstrong, James R.en_US
dc.contributor.committeememberGray, Festus Gailen_US
dc.contributor.committeememberHa, Dong Samen_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-10062009-020040/en_US
dc.date.sdate2009-10-06en_US
dc.date.rdate2009-10-06
dc.date.adate2009-10-06en_US


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