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dc.contributor.authorAl-Mahmood, Saiyid Jami Islah Ahmaden_US
dc.date.accessioned2014-03-14T21:48:42Z
dc.date.available2014-03-14T21:48:42Z
dc.date.issued1990-01-03en_US
dc.identifier.otheretd-11012008-063423en_US
dc.identifier.urihttp://hdl.handle.net/10919/45402
dc.description.abstract

VLSI technology is continually fueling the need for more efficient computer aided design tools. Parallel or distributed processing is a possible solution to this problem. Advances in computer networking have made distributed processing over a local area network very attractive and cost-effective. This research investigates the application of such a large-grained parallel processing method to the task of checking geometric constraints or design rules that are imposed on the layout of VLSI circuits to ensure a correct implementation of the design despite imperfections in the fabrication process.

The thesis begins with a study of design rule checking algorithms including algorithms for parallel processing as applied to design rule checking. Then, the algorithms for a technology independent design rule verification tool are developed. For distributed processing, two separate approaches are examined. One approach, called the data partitioning method, divides a fully instantiated or non-hierarchical layout into several sections and then processes each section on a different computer. The second approach looks for smaller tasks within the design rule checking process that can be executed in parallel and is called the task partitioning method. A dynamic task-scheduling algorithm is used to assign the tasks to the available processors. Implementations of both of these parallel processing schemes on a local area network of workstations are described. Experiments are performed to assess the performance of the programs and the results of testing a few layouts are presented.

en_US
dc.format.mediumBTDen_US
dc.publisherVirginia Techen_US
dc.relation.haspartLD5655.V855_1990.A425.pdfen_US
dc.subjectIntegrated circuitsen_US
dc.subject.lccLD5655.V855 1990.A425en_US
dc.titleA distributed design rule checker for VLSI layoutsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineElectrical Engineeringen_US
dc.contributor.committeechairMidkiff, Scott F.en_US
dc.contributor.committeememberNunnally, Charles E.en_US
dc.contributor.committeememberTront, Joseph G.en_US
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11012008-063423/en_US
dc.date.sdate2008-11-01en_US
dc.date.rdate2008-11-01
dc.date.adate2008-11-01en_US


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