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dc.contributor.authorDobson, Christopher Vanessen_US
dc.date.accessioned2014-07-17T08:00:09Z
dc.date.available2014-07-17T08:00:09Z
dc.date.issued2014-07-16en_US
dc.identifier.othervt_gsexam:3471en_US
dc.identifier.urihttp://hdl.handle.net/10919/49579
dc.description.abstractThe rapid rise in computational performance offered by computer systems has greatly increased the number of practical software defined radio applications. The addition of FPGAs to these flexible systems has resulted in platforms that can address a multitude of applications with performance levels that were once only known to ASICs. This work presents an embedded heterogeneous scalable cluster platform with software defined radio applications. The Xilinx Zynq chip provides a hybrid platform consisting of an embedded ARM general-purpose processing core and a low-power FPGA. The ARM core provides all of the benefits and ease of use common to modern high-level software languages while the FPGA segment offers high performance for computationally intensive components of the application. Four of these chips were combined in a scalable cluster and a task assigner was written to automatically place data flows across the FPGAs and ARM cores. The rapid reconfiguration software tFlow was used to dynamically build arbitrary FPGA images out of a library of pre-built modules.en_US
dc.format.mediumETDen_US
dc.publisherVirginia Techen_US
dc.rightsThis Item is protected by copyright and/or related rights. Some uses of this Item may be deemed fair and permitted by law even without permission from the rights holder(s), or the rights holder(s) may have licensed the work for use under certain conditions. For other uses you need to obtain permission from the rights holder(s).en_US
dc.subjectZynqen_US
dc.subjecttFlowen_US
dc.subjectSoftware Defined Radioen_US
dc.subjectCognitive Radioen_US
dc.titleAn Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applicationsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreeMaster of Scienceen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelmastersen_US
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen_US
thesis.degree.disciplineComputer Engineeringen_US
dc.contributor.committeechairAthanas, Peter M.en_US
dc.contributor.committeememberSchaumont, Patrick Roberten_US
dc.contributor.committeememberMcGwier, Robert W.en_US


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